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參數(shù)資料
| 型號(hào)： | SY89833ALMGTR |
| 廠商： | MICREL INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | 89833 SERIES, LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), QCC16 |
| 封裝： | 3 X 3 MM, LEAD FREE, MLF-16 |
| 文件頁(yè)數(shù)： | 6/12頁(yè) |
| 文件大?。?/td> | 413K |
| 代理商： | SY89833ALMGTR |
Micrel, Inc.
SY89833AL
March 2009
3
M9999-032609-A
hbwhelp@micrel.com or (408) 955-1690
Pin Description
Pin Number
Pin Name
Pin Function
15, 16
1, 2
3, 4
5, 6
Q0, /Q0
Q1, /Q1
Q2, /Q2
Q3, /Q3
LVDS Differential Outputs: Normally terminated with 100 across the pair (Q,
/Q). See “LVDS Outputs” section, Figure 2a. Unused outputs should be
terminated with a 100 resistor across each pair.
8
EN
This single-ended TTL/CMOS-compatible input functions as a synchronous
output enable. The synchronous enable ensures that enable/disable will only
occur when the outputs are in a logic LOW state. Note that this input is internally
connected to a 25k pull-up resistor and will default to logic HIGH state
(enabled) if left open.
9, 12
/IN, IN
Differential Input: This input pair is the differential signal input to the device.
Input accepts AC- or DC-Coupled differential signals as small as 100mV. Each
pin of the pair internally terminates to a VT pin through 50. Note that this input
will default to an intermediate state if left open. Please refer to the “Input
Interface Applications” section for more details.
10
VREF-AC
Reference Voltage: This output biases to VCC–1.4V. It is used when AC-
Coupling the input (IN, /IN). For AC-Coupled applications, connect VREF-AC to
VT pin and bypass with 0.1F low ESR capacitor to VCC. See “Input Interface
Applications” section for more details. Maximum sink/source current is ±1.5mA.
Due to the limited drive capability, each VREF-AC pin is only intended to drive its
respective VT pin.
11
VT
Input Termination Center-Tap: Each side of the differential input pair terminates
to the VT pin. The VT pin provides a center-tap to a termination network for
maximum interface flexibility. See “Input Interface Applications” section for more
details.
13
GND
Ground. GND pin and exposed pad must be connected to the most negative
potential of the device ground.
7, 14
VCC
Positive Power Supply: Bypass with 0.1F//0.01F low ESR capacitors and
place as close to each VCC pin as possible.
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