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參數(shù)資料
| 型號： | SY89837UMTR |
| 廠商： | MICREL INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 89837 SERIES, LOW SKEW CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), QCC32 |
| 封裝： | 5 X 5 MM, MLF-32 |
| 文件頁數(shù)： | 9/14頁 |
| 文件大小： | 179K |
| 代理商： | SY89837UMTR |
4
SY89837U
Micrel
M9999-091404
hbwhelp@micrel.com or (408) 955-1690
DETAILED FUNCTIONAL DESCRIPTION
RPE MUX and Fail-Safe Input
The SY89837U is optimized for clock switchover
applications where switching from one clock to another clock
without runt pulses (short cycles) is required. It features two
unique circuits:
1. Runt-Pulse Eliminator (RPE) Circuit
The RPE MUX provides a “glitchless” switchover between
two clocks and prevents any runt pulses from occurring
during the switchover transition. The design of both clock
inputs is identical (i.e., the switchover sequence and
protection is symmetrical for both input pair, IN0 or IN1.
Thus, either input pair may be defined as the primary input).
If not required, the RPE function can be permanently
disabled to allow the switchover between inputs to occur
immediately. For more detail on how to disable the RPE
function within the MUX, see the “Power-On Reset (POR)”
section.
2. Fail-Safe Input (FSI) Circuit
The FSI function provides protection against a selected
input pair that drops below the minimum amplitude
requirement. If the selected input pair drops sufficiently below
the 200mV minimum single-ended input amplitude limit (VIN),
or 400mV differentially (Vdiff_IN), the output will latch to the
last valid clock state.
RPE and FSI Functionality
The basic operation of the RPE MUX and FSI functionality
is described with the following four case descriptions. All
descriptions are related to the true inputs and outputs. The
primary (or selected) clock is called CLK1, the secondary
(or alternate) clock is called CLK2. Due to the totally
asynchronous relation of the IN and SEL signals and an
additional internal protection against metastability, the
number of pulses required for the operations described in
cases 1 through 4 can vary within certain limits. Refer to
“Timing Diagrams” and “Applications” section for detailed
information.
Case #1 Two Normal Clocks and RPE Enabled.
In this case the frequency difference between the two
running clocks IN0 and IN1 must not be greater than 1.5:1.
For example, if the IN0 clock is 500MHz, the IN1 clock
must be within the range of 334MHz to 750MHz.
If the SEL input changes state to select the alternate
clock, the switchover from CLK1 to CLK2 will occur in three
stages:
Stage 1: The output will continue to follow CLK1
for a limited number of pulses.
Stage 2: The output will remain LOW for a
limited number of pulses of CLK2.
Stage 3: The output follows CLK2.
CLK1
CLK2
SEL
OUTPUT
Select CLK1
Stage 1
Stage 2
Stage 3
Select CLK2
3 to 5 falling edges
of CLK1
4 to 5 falling edges
of CLK2
Runt pulse eliminated
from output
Figure 2. Timing Diagram 1
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SY89838U | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:Precision 1:8 LVDS Clock Fanout Buffer with 2:1 Runt Pulse Eliminator Input MUX |
| SY89838U_10 | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:Precision 1:8 LVDS Clock Fanout Buffer |
| SY89838UMG | 功能描述:編碼器、解碼器、復(fù)用器和解復(fù)用器 Ultra-low Jitter 1:8 Any-In to LVDS Fanout with 2:1 RPE/FSI Input MUX with Internal Termination RoHS:否 制造商:Micrel 產(chǎn)品:Multiplexers 邏輯系列:CMOS 位數(shù): 線路數(shù)量（輸入/輸出）:2 / 12 傳播延遲時間:350 ps, 400 ps 電源電壓-最大:2.625 V, 3.6 V 電源電壓-最小:2.375 V, 3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-44 封裝:Tray |
| SY89838UMG TR | 功能描述:編碼器、解碼器、復(fù)用器和解復(fù)用器 Ultra-low Jitter 1:8 Any-In to LVDS Fanout with 2:1 RPE/FSI Input MUX with Internal Termination RoHS:否 制造商:Micrel 產(chǎn)品:Multiplexers 邏輯系列:CMOS 位數(shù): 線路數(shù)量（輸入/輸出）:2 / 12 傳播延遲時間:350 ps, 400 ps 電源電壓-最大:2.625 V, 3.6 V 電源電壓-最小:2.375 V, 3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-44 封裝:Tray |
| SY89838UMGTR | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:Precision 1:8 LVDS Clock Fanout Buffer with 2:1 Runt Pulse Eliminator Input MUX |
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