參數(shù)資料
型號(hào): SY89838UMG
廠商: Micrel Inc
文件頁(yè)數(shù): 4/9頁(yè)
文件大?。?/td> 0K
描述: IC CLK BUFF MUX 2:8 2GHZ 32-MLF
標(biāo)準(zhǔn)包裝: 60
系列: Precision Edge®
類(lèi)型: 扇出緩沖器(分配),多路復(fù)用器
電路數(shù): 1
比率 - 輸入:輸出: 2:8
差分 - 輸入:輸出: 是/是
輸入: CML,LVDS,LVPECL
輸出: LVDS
頻率 - 最大: 2GHz
電源電壓: 2.375 V ~ 2.625 V
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 32-VFQFN 裸露焊盤(pán),32-MLF?
供應(yīng)商設(shè)備封裝: 32-MLF?(5x5)
包裝: 管件
產(chǎn)品目錄頁(yè)面: 1084 (CN2011-ZH PDF)
其它名稱(chēng): 576-1538-5
SY89838UMG-ND
Micrel, Inc.
SY89838U
May 2008
M9999-051308-D
hbwhelp@micrel.com or (408) 955-1690
4
Pin Description
Pin Number
Pin Name
Pin Function
1, 3,
6, 8
IN0, /IN0,
IN1, /IN1
Differential Inputs: These input pairs are the differential signal inputs to the
device. These inputs accept AC or DC-coupled signals as small as 100mV
(200mVPP). Each pin of a pair internally terminates to a VT pin through 50.
Please refer to the “Input Interface Applications” section for more details.
2, 7
VT0, VT1
Input Termination Center-Tap: Each side of the differential input pair terminates
to a VT pin. The VT0 and VT1 pins provide a center-tap to a termination network
for maximum interface flexibility. See the “Input Interface Applications” section
for more details.
31
SEL
This single-ended TTL/CMOS-compatible input selects the inputs to the
multiplexer. Note that this input is internally connected to a 25k pull-up resistor
and will default to a logic HIGH state if left open. Input threshold is VCC/2.
9, 19, 22, 32
VCC
Positive Power Supply: Bypass with 0.1F//0.01F low ESR capacitors as close
to VCC pins as possible.
30, 28, 26, 24,
18, 16, 14, 12,
29, 27, 25, 23,
17, 15, 13, 11
Q0 – Q7,
/Q0 – /Q7
Differential Outputs: These LVDS output pairs are a logic function of the IN0,
IN1, and SEL inputs. Please refer to the truth table below for details. Unused
output pairs must be terminated with 100 across the pair.
20, 21
GND,
Exposed Pad
Ground: Ground pin and exposed pad must be connected to the same ground
plane.
10
CAP
Power-On Reset (POR) Initialization capacitor. When using the multiplexer with
RPE capability, this pin is tied to a capacitor to VCC. The purpose is to ensure
the internal RPE logic starts up in a known state. See “Power-On Rest (POR)
Description” section for more details regarding capacitor selection. If this pin is
tied directly to VCC, the RPE function will be disabled and the multiplexer will
function as a normal multiplexer. The CAP pin should never be left open.
4, 5
VREF-AC0
VREF-AC1
Reference Voltage: These outputs bias to VCC–1.2V. They are used for AC-
coupling inputs (IN, /IN). Connect VREF_AC directly to the VT pin. Bypass with
0.01F low ESR capacitor to VCC. See “Input Interface Applications” section.
Maximum sink/source current is ±1.5mA.
Truth Table
Inputs
Outputs
IN0
/IN0
IN1
/IN1
SEL
Q
/Q
0
1
X
0
1
0
X
0
1
0
X
0
1
0
1
X
1
0
1
0
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