參數(shù)資料
| 型號： | SY89873LMG TR |
| 廠商： | Micrel Inc |
| 文件頁數(shù)： | 1/11頁 |
| 文件大小： | 0K |
| 描述： | IC CLK BUFF DVDR 1:3 2GHZ 16-MLF |
| 標準包裝： | 1,000 |
| 系列： | Precision Edge® |
| 類型： | 扇出緩沖器（分配），除法器 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:3 |
| 差分 - 輸入:輸出： | 是/是 |
| 輸入： | CML，HSTL，LVDS，LVPECL |
| 輸出： | LVDS |
| 頻率 - 最大： | 2GHz |
| 電源電壓： | 2.97 V ~ 3.63 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-VFQFN 裸露焊盤，16-MLF? |
| 供應商設備封裝： | 16-MLF?（3x3） |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | SY89873LMGTR SY89873LMGTR-ND |
1
Precision Edge
SY89873L
Micrel, Inc.
M9999-082407
hbwhelp@micrel.com or (408) 955-1690
DESCRIPTION
Guaranteed AC performance
> 2.0GHz fMAX output toggle
> 3.0GHz fMAX input
< 800ps tPD (matched-delay between banks)
< 15ps within-device skew
< 190ps rise/fall time
Low jitter design
< 1psRMS cycle-to-cycle jitter
Unique input termination and VT pin for DC-coupled
and AC-coupled inputs: any differential inputs
(LVPECL, LVDS, CML, HSTL)
Precision differential LVDS outputs
Matched delay: all outputs have matched delay,
independent of divider setting
TTL/CMOS inputs for select and reset/disable
Two LVDS output banks (matched delay)
Bank A: Buffered copy of input clock (undivided)
Bank B: Divided output (÷2, ÷4, ÷8, ÷16),
two copies
3.3V power supply
Wide operating temperature range: –40°C to +85°C
Available in 16-pin (3mm ××××× 3mm) QFN package
FEATURES
3.3V, 2.0GHz ANY DIFF. IN-TO-LVDS
PROGRAMMABLE CLOCK DIVIDER
FANOUT BUFFER W/ INTERNAL TERMINATION
Precision Edge
SY89873L
APPLICATIONS
SONET/SDH line cards
Transponders
High-end, multiprocessor servers
Rev.: F
Amendment: /0
Issue Date: February 2007
This 3.3V low-skew, low-jitter, precision LVDS output clock
divider accepts any high-speed differential clock input (AC- or
DC-coupled) CML, LVPECL, HSTL or LVDS and divides down
the frequency using a programmable divider ratio to create a
frequency-locked, lower speed version of the input clock. The
SY89873L includes two output banks. Bank A is an exact
copy of the input clock (pass through) with matched
propagation delay to Bank B, the divided output bank. Available
divider ratios are 2, 4, 8 and 16. In a typical 622MHz clock
system this would provide availability of 311MHz, 155MHz,
77MHz or 38MHz auxiliary clock components.
The differential input buffer has a unique internal termination
design that allows access to the termination network through
a VT pin. This feature allows the device to easily interface to
all AC- or DC-coupled differential logic standards. A VREF-AC
reference is included for AC-coupled applications.
The SY89873L is part of Micrel’s high-speed Precision
Edge timing and distribution family. For 2.5V applications,
consider the SY89872U. For applications that require an
LVPECL output, consider the SY89871U.
The /RESET input asynchronously resets the divider outputs
(Bank B). In the pass-through function (Bank A) the /RESET
synchronously enables or disables the outputs on the next
falling edge of IN (rising edge of /N). Refer to the Timing
Diagram.
All support documentation can be found on Micrel’s web
site at: www.micrel.com.
FUNCTIONAL BLOCK DIAGRAM
TYPICAL APPLICATION
Precision Edge is a registered trademark of Micrel, Inc.
IN
50
/IN
S0
S1
QB1
/QB1
QB0
/QB0
QA
/QA
/RESET
VT
VREF-AC
Divided
by
2, 4, 8
or 16
Decoder
Enable
FF
Enable
MUX
Precision Edge
IN
/IN
QA
/QA
622MHz LVDS
Clock Out
622MHz LVPECL
Clock In
622MHz/155.5MHz
SONET Clock Generator
Bank B: 155.5MHz: For OC-3 line card
Set to divide-by-4
Bank A: 622MHz: For OC-12 line card
Set to pass-through
155.5MHz LVDS
Clock Out
OC-12 or
OC-3
Clock Gen
QB
/QB
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| SY89873LMI | 功能描述:IC CLK BUFF DVDR 1:3 2GHZ 16-MLF RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘緩沖器，驅動器 系列:Precision Edge® 標準包裝:1 系列:HiPerClockS™ 類型:扇出緩沖器（分配），多路復用器 電路數(shù):1 比率 - 輸入:輸出:2:18 差分 - 輸入:輸出:是/無 輸入:CML，LVCMOS，LVPECL，LVTTL，SSTL 輸出:LVCMOS，LVTTL 頻率 - 最大:250MHz 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應商設備封裝:32-TQFP（7x7） 包裝:- 其它名稱:800-1923-6 |
| SY89873LMI TR | 功能描述:IC CLK BUFF DVDR 1:3 2GHZ 16-MLF RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘緩沖器，驅動器 系列:Precision Edge® 標準包裝:1 系列:HiPerClockS™ 類型:扇出緩沖器（分配），多路復用器 電路數(shù):1 比率 - 輸入:輸出:2:18 差分 - 輸入:輸出:是/無 輸入:CML，LVCMOS，LVPECL，LVTTL，SSTL 輸出:LVCMOS，LVTTL 頻率 - 最大:250MHz 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應商設備封裝:32-TQFP（7x7） 包裝:- 其它名稱:800-1923-6 |
| SY89873LMITR | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:3.3V, 2.0GHz ANY DIFF. IN-TO-LVDS PROGRAMMABLE CLOCK DIVIDER FANOUT BUFFER W/ INTERNAL TERMINATION |
| SY89874AUMG | 功能描述:時鐘驅動器及分配 2.5GHz Programmable Clock Divider/Fanout Buffer RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| SY89874AUMG TR | 功能描述:時鐘驅動器及分配 2.5GHz Programmable Clock Divider/Fanout Buffer RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
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