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參數(shù)資料
| 型號(hào)： | SYS32512LKLI-30 |
| 英文描述： | Ultra Low Capacitance Transient Voltage Suppressor Diodes |
| 中文描述： | X32號(hào)的SRAM模塊 |
| 文件頁(yè)數(shù)： | 5/7頁(yè) |
| 文件大小： | 206K |
| 代理商： | SYS32512LKLI-30 |
SYS321000ZK/LK - 012/015/20/25
ISSUE 1.5 : December 1998
5
Read Cycle Timing Waveform
(1,2)
Write Cycle No.1 Timing Waveform
(1,4)
t
WR(7)
AS(6)
t
CW
t
WP(2)
High-Z
t
DW
DH
AW
Don't
Care
t
t
t
t
t
WC
OHZ(3,9)
Address
OE
CS1~4
WE
Dout
Din
High-Z
OW
t
(8)
Data Valid
OE
t
ACS
t
CLZ (4,5)
t
OHZ (3)
t
t
OLZ
AA
OH
CHZ (3,4,5)
Data Valid
t
t
t
t
RC
Address
CS1~4
Dout
OE
Don't
care.
AC Read Characteristics Notes
(1) WE is High for Read Cycle.
(2) All read cycle timing is referenced from the last valid address to the first transition address.
(3) t
CHZ
and t
OHZ
are defined as the time at which the outputs achieve open circuit conditions and are not
referenced to output voltage levels.
(4) At any given temperature and voltage condition, t
CHZ
(max) is less than t
CLZ
(min) both for a given module
and from module to module.
(5) These parameters are sampled and not 100% tested.
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