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| 型號： | SYS8512FKXI-12 |
| 英文描述： | 512K x 8 SRAM MODULE |
| 中文描述： | 為512k × 8的SRAM模塊 |
| 文件頁數(shù)： | 6/7頁 |
| 文件大?。?/td> | 69K |
| 代理商： | SYS8512FKXI-12 |
ISSUE 5.0 November 1999
SYS8512FKX-70/85/10/12
6
Write Cycle No.2 Timing Waveform
AC Characteristics Notes
(1) A write occurs during the overlap (t
WP
) of a low CS and a low WE.
(2) t
CW
is measured from the earlier of CS or WE going high to the end of write cycle.
(3) t
AS
is measured from the address valid to the beginning of write.
(4) t
WR
is measured from the earliest of CS or WE going high to the end of write.
(5) During this period, I/O pins are in the output state. Input signals out of phase must not be applied.
(6) If CS goes low simultaneously with WE going low or after WE going low , outputs remain in a high impedance state.
(7) D
OUT
is in the same phase as written data of this write cycle.
(8) D
OUT
is the read data of next address.
(9) If CS is low during this period, I/O pins are in the output state, and inputs out of phase must not be applied to I/O pins.
(10) This parameter is sampled and not 100% tested.
(11) t
is defined as the time at which the outputs achieve open circuit conditions and is not referenced to output voltage
levels. This parameter is sampled and not 100% tested.
CW (2)
WR (4)
WC
t
AS (3)
DW
DH
OH
t
OW
WHZ(5)
AW
WP (1)
Don't
Care
t
t
t
t
t
Address
CS
WE
Dout
Din
t
t
t
t
High-Z
High-Z
(7)
(8)
Data Retention Waveform
t
R
t
CDR
4.5V
2.2V
4.5V
2.2V
0V
DATA RETENTION MODE
Vcc
CS
V
DR
CS > Vcc -0.2V
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| SYS8512FKXI-70 | 512K x 8 SRAM MODULE |
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| SYS8512FKXI-70 | 制造商:MOSAIC 制造商全稱:MOSAIC 功能描述:512K x 8 SRAM MODULE |
| SYS8512FKXI-85 | 制造商:MOSAIC 制造商全稱:MOSAIC 功能描述:512K x 8 SRAM MODULE |
| SYS8512FKXL-10 | 制造商:MOSAIC 制造商全稱:MOSAIC 功能描述:512K x 8 SRAM MODULE |
| SYS8512FKXL-12 | 制造商:MOSAIC 制造商全稱:MOSAIC 功能描述:512K x 8 SRAM MODULE |
| SYS8512FKXL-70 | 制造商:MOSAIC 制造商全稱:MOSAIC 功能描述:512K x 8 SRAM MODULE |
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