參數(shù)資料
型號: SYS8512FKXI-85
英文描述: 512K x 8 SRAM MODULE
中文描述: 為512k × 8的SRAM模塊
文件頁數(shù): 3/7頁
文件大?。?/td> 69K
代理商: SYS8512FKXI-85
SYS8512FKX-70/85/10/12
ISSUE 5.0 November 1999
3
Capacitance
(V
CC
=5V±10%,T
A
=25
o
C)
Note: Capacitance calculated, not measured.
Operation Truth Table
Low V
cc
Data Retention Characteristics - L Version Only
Parameter
Symbol
Test Condition
max
Unt
Input Capacitance (CS, A17, A18)
I/P Capacitance (other)
I/O Capacitance
C
IN1
C
IN2
C
I/O
V
IN
= 0V
V
IN
= 0V
V
I/O
= 0V
10
40
40
pF
pF
pF
CS
OE
WE
DATA PINS
SUPPLY CURRENT
MODE
H
X
X
High Impedance
I
SB1
, I
SB2
Standby
L
L
H
Data Out
I
CC1
, I
CC2
I
CC1
, I
CC2
Read
L
L
L
Data In
Write
L
H
L
Data In
I
CC1
, I
CC2
Write
Notes : H = V
IH
: L =V
IL
: X = V
IH
or V
IL
-L Part
Parameter
Symbol
Test Condition
mn
typ
(1)
max
V
CC
for Data Retention
Data Retention Current
V
DR
CS - V
CC
-0.2V
2.0
-
-
V
CC
= 3.0V, CS = V
CC
-0.2V
I
CCDR2
I
CCDR3
T
OP
= 0C to 70C
-
9
230
μA
T
OP
= T
AI
-
-
310
μA
Chip Deselect to
Data Retention Time
t
CDR
t
R
See Retention Waveform
0
-
-
0
-
-
ns
Operation Recovery Time
See Retention Waveform
5
-
-
0
-
-
ms
Notes (1) Typical figures are measured at 25°C.
(2) This parameter is guaranteed not tested.
* Input pulse levels: 0V to 3.0V
* Input rise and fall times: 5ns
* Input and Output timing reference levels: 1.5V
* Output load: see diagram
* V
CC
=5V±10%
AC Test Conditions
Output Load
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