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參數(shù)資料
| 型號(hào)： | SZA-5044 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 4.9 - 5.9 GHz 5V Power Amplifier |
| 中文描述： | 4月9日至5月九日吉赫5V電源放大器 |
| 文件頁數(shù)： | 2/8頁 |
| 文件大?。?/td> | 267K |
| 代理商： | SZA-5044 |
303 South Technology Court Broomfield, CO 80021
Phone: (800) SMI-MMIC
2
http://www.sirenza.com
EDS-103585 Rev C
Preliminary
SZA-5044 4.9-5.9 GHz Power Amp
Pin Out Description
Pin #
Function
Description
1,3,5,9,
11,15,17
N/C
Pins are not used. May be grounded, left open, or connected to adjacent pin.
6
VPC1
VPC1 is the bias control pin for the stage 1 active bias circuit and can be run from 2.9V to 5V control. An exter-
nal series resistor is required for proper setting of bias levels depending on control voltage. Refer to the evalu-
ation board schematic for resistor value. To prevent potential damage, do not apply voltage to this pin that is
+1V greater than voltage applied to pin 20 (Vbias) unless Vpc supply current capability is less than 10 mA.
7
VPC2
VPC2 is the bias control pin for the stage 2 active bias circuit and can be run from 2.9V to 5V control. An exter-
nal series resistor is required for proper setting of bias levels depending on control voltage. Refer to the evalu-
ation board schematic for resistor value. To prevent potential damage, do not apply voltage to this pin that is
+1V greater than voltage applied to pin 20 (Vbias) unless Vpc supply current capability is less than 10 mA.
8
VPC3
VPC3 is the bias control pin for the stage 3 active bias circuit and can be run from 2.9V to 5V control. An exter-
nal series resistor is required for proper setting of bias levels depending on control voltage. Refer to the evalu-
ation board schematic for resistor value. To prevent potential damage, do not apply voltage to this pin that is
+1V greater than voltage applied to pin 20 (Vbias) unless Vpc supply current capability is less than 10 mA.
10
Vdet
Ouput power detector voltage. Load with 10K-100K ohms to ground for best performance.
2,4
RFIN
RF input pins. This is DC grounded internal to the IC. Do not apply voltage to this pin. All three pins must be
used for proper operation.
12,13,14
RFOUT
RF output pin. This is also another connection to the 3rd stage collector
16
VC3
3rd stage collector bias pin. Apply 5V to this pin.
18
VC2
2nd stage collector bias pin. Apply 5V to this pin.
19
VC1
1st stage collector bias pin. Apply 5V to this pin.
20
Vbias
Active bias network VCC. Apply 5V to this pin.
EPAD
Gnd
Exposed area on the bottom side of the package needs to be soldered to the ground plane of the board for
optimum thermal and RF performance. Several vias should be located under the EPAD as shown in the rec-
ommended land pattern (page 5).
Caution: ESD Sensitive
Appropriate precaution in handling, packaging
and testing devices must be observed.
Absolute Maximum Ratings
Parameters
Value
Unit
VC3 Collector Bias Current (pin16)
500
mA
VC2 Collector Bias Current (pin18)
225
mA
VC1 Collector Bias Current (pin19)
75
mA
Device Voltage (V
D
)
Power Dissipation
7.0
V
3.4
W
Operating Lead Temperature (T
L
)
RF Input Power for 50 ohm RF out load
-40 to +85
oC
15
dBm
RF Input Power for 10:1 VSWR RF out
load
2
dBm
Storage Temperature Range
-40 to +150
oC
Operating Junction Temperature (T
J
)
ESD Human Body Model
+150
oC
>1000
V
Operation of this device beyond any one of these limits may
cause permanent damage. For reliable continuous operation
the device voltage and current must not exceed the maximum
operating values specified in the table on page one.
Bias conditions should also satisfy the following expression:
I
D
V
D
< (T
J
- T
L
) / R
TH’
j-l
Simplified Device Schematic
Stage 1
Bias
Stage 2
Bias
Stage 3
Bias
Pin 2, 4
Pin 12,13,14
Pin
6
Pin
20
Pin
19
Pin
7
Pin
18
Pin
8
Pin
16
Pin
10
EPAD
EPAD
EPAD
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