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參數(shù)資料
| 型號(hào)： | T15M256B-85RI |
| 廠商： | TM Technology, Inc. |
| 英文描述： | 32K X 8 LOW POWER CMOS STATIC RAM |
| 中文描述： | 32K的× 8低功耗CMOS靜態(tài)RAM |
| 文件頁數(shù)： | 5/13頁 |
| 文件大?。?/td> | 87K |
| 代理商： | T15M256B-85RI |
TE
CH
tm
AC CHARACTERISTICS
(
Vcc
= 5V /
± 10%
, Vss = 0V, Ta =
0 ~ +70
°
C/
-40 to 85
°
C)
(1) READ CYCLE
T15M256B
TM Technology Inc. reserves the right
P. 5
to change products or specifications without notice.
Publication Date: MAY. 2002
Revision:A
-50ns
-70ns
-85ns
-100ns
PARAMETER
SYM.
MIN MAX MIN. MAX. MIN. MAX. MIN. MAX.
50
-
70
-
UNIT
Read Cycle Time
t
RC
t
AA
t
ACS
t
AOE
t
CLZ*
t
OLZ*
85
-
100
-
ns
Address Access Time
-
50
-
70
-
85
-
100
ns
Chip Select Access Time
-
50
-
70
-
85
-
100
ns
Output Enable to Output Valid
-
25
-
35
-
40
-
50
ns
Chip Selection to Output in Low Z
7
-
10
-
10
-
10
-
ns
Output Enable to Output in Low Z
Chip Deselection to Output in High Z
t
CHZ*
5
-
5
-
5
-
5
-
ns
-
20
-
25
-
30
-
30
ns
Output Disable to Output in High Z
t
OHZ*
t
OH
-
20
-
25
-
30
-
30
ns
Output Hold from Address Change
10
-
10
-
10
-
10
-
ns
* These parameters is measured with 5pF test load.
(2)WRITE CYCLE
-50ns
-70ns
-85ns
-100ns
PARAMETER
SYM.
MIN MAX MIN. MAX. MIN. MAX. MIN. MAX.
50
-
70
-
UNIT
Write Cycle Time
t
WC
t
CW
t
AW
85
-
100
-
ns
Chip Selection to End of Write
40
-
60
-
70
-
80
-
ns
Address Valid to End of Write
40
-
60
-
70
-
80
-
ns
Address Setup Time
t
AS
t
WP
t
WR
t
DW
t
DH
t
WHZ*
t
OW
0
-
0
-
0
-
0
-
ns
Write Pulse Width
30
-
50
-
60
-
70
-
ns
Write Recovery Time
0
-
0
-
0
-
0
-
ns
Data Valid to End of Write
25
-
30
-
35
-
40
-
ns
Data Hold from End of Write
0
-
0
-
0
-
0
-
ns
Write to Output in High Z
-
20
-
25
-
30
-
30
ns
Output Active from End of Write
5
-
5
-
5
-
5
-
ns
* These parameters is measured with 30pF test load.
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