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參數(shù)資料
| 型號(hào)： | T15M64A-100N |
| 廠商： | TM Technology, Inc. |
| 英文描述： | 8K X 8 LOW POWER CMOS STATIC RAM |
| 中文描述： | 8K的× 8低功耗CMOS靜態(tài)RAM |
| 文件頁(yè)數(shù)： | 9/13頁(yè) |
| 文件大?。?/td> | 87K |
| 代理商： | T15M64A-100N |
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TE
CH
tm
Notes: 1. During this period, I/O pins are in the output state, so input signals of opposite phase to the
outputs should not be applied.
2. The data output from
D
OUT
are the same as the data written to
D
IN
during the write cycle.
3.
D
OUT
provides the read data for the next address.
4. Transition is measured
±
500 mV from steady state with
C
L
= 5pF. This parameter is
guaranteed but not 100% tested.
Preliminary T15M64A
TM Technology Inc. reserves the right
P. 9
to change products or specifications without notice.
Publication Date: SEP. 2002
Revision:0.A
5. If OE is low during a WE controlled write cycle, the write pulse width must be the larger of
tWP or (tWHZ + tDW) to allow the I/O drivers to turn off and data to be placed on the bus for the
required tDW. If OE is high during a WE controlled write cycle, this requirement does
not apply and the write pulse can be as short as the specified tWP.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| T15M64A-100P | 8K X 8 LOW POWER CMOS STATIC RAM |
| T15N1024A | CAP 560UF 450V ELECT TS-UQ |
| T15N1024A-100C | CAP 680UF 450V ELECT TSUQ |
| T15N1024A-100CI | 128K X 8 LOW POWER CMOS STATIC RAM |
| T15N1024A-100P | 128K X 8 LOW POWER CMOS STATIC RAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| T15M64A-100P | 制造商:TMT 制造商全稱:TMT 功能描述:8K X 8 LOW POWER CMOS STATIC RAM |
| T15N1 | 制造商:EDAL 制造商全稱:EDAL 功能描述:T10A1 |
| T15N1024A | 制造商:TMT 制造商全稱:TMT 功能描述:128K X 8 LOW POWER CMOS STATIC RAM |
| T15N1024A-100C | 制造商:TMT 制造商全稱:TMT 功能描述:128K X 8 LOW POWER CMOS STATIC RAM |
| T15N1024A-100CI | 制造商:TMT 制造商全稱:TMT 功能描述:128K X 8 LOW POWER CMOS STATIC RAM |
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