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參數資料
| 型號： | T4223B-MF |
| 廠商： | ATMEL CORP |
| 元件分類： | 消費家電 |
| 英文描述： | Time-Code Receiver with A/D Converter |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, UUC22 |
| 封裝： | DIE-22 |
| 文件頁數： | 4/18頁 |
| 文件大?。?/td> | 138K |
| 代理商： | T4223B-MF |
U4223B
Rev. A7, 06-Mar-01
4 (18)
Q2A, Q2B
According to Q1A/Q1B, a crystal is connected between
the Pins Q2A and Q2B. It is used with the serial resonant
frequency of the time-code transmitter (e.g., 60 kHz
WWVB, 77.5 kHz DCF or 40 kHz JG2AS). The equiva-
lent parallel capacitor of the filter crystal is internally
compensated. The value of the compensation is about
0.7 pF.
Q2A
Q2B
GND
Figure 11.
PON
If PON is connected to GND, the receiver will be
activated. The set-up time is typically 0.5 s after applying
GND at this pin. If PON is connected to VCC, the receiver
will switch to power-down mode.
VCC
PON
Figure 12.
D0, D1, D2, D3
The outputs of the ADC consist of PNP-NPN push-pull
stages and can be directly connected to a microcomputer.
In order to avoid any interference of the output into the
antenna circuit, we recommend terminating each digital
output with a capacitor of 10 nF. The digitalized signal of
the ADC is Gray coded (see table). It should be taken into
account that in power-down mode (PON = high), D0, D1,
D2 and D3 will be high.
A sequence of the digitalized time-code signal can be
analyzed by a special noise-suppressing algorithm in
order to increase the sensitivity and the signal-to-noise
ratio (more than 10 dB compared to conventional
decoding). Details about the time-code format are
described separately.
Decimal
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Gray
0000
0001
0011
0010
0110
0111
0101
0100
1100
1101
1111
1110
1010
1011
1001
1000
VCC
D0 ... D3
GND
PON
Figure 13.
CLK
The input of the ADC is switched to the AGC voltage by
the rising slope of the clock. When conversion time has
passed (about 1.8 ms at 25
°
C), the digitalized field-
strength signal is stored in the output registers D0 to D3
as long as the clock is high and can be read by a micro-
computer. The falling slope of the clock switches the
input of the ADC to the time-code signal. In the mean-
time, the digitalized time-code signal is stored in the
output registers D0 to D3 as long as the clock is low (see
figure 14).
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