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參數(shù)資料
| 型號： | T436416A-10SG |
| 廠商： | TM Technology, Inc. |
| 英文描述： | Terminal Block End Barrier; For Use With:AB1 Series Terminal Blocks; Accessory Type:End Barrier; Leaded Process Compatible:Yes; Peak Reflow Compatible (260 C):Yes RoHS Compliant: Yes |
| 中文描述： | 4米× 16內(nèi)存 |
| 文件頁數(shù)： | 17/29頁 |
| 文件大?。?/td> | 712K |
| 代理商： | T436416A-10SG |
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TE
CH
tm
Page Read & Write Cycle at Same Bank @ Burst Length = 4
0
1
2
3
4
5
T436416A
TM Technology Inc. reserves the right
P.17
to change products or specifications without notice.
Publication Date: MAY. 2003
Revision: B
C L O C K
C K E
C S
R A S
C A S
A D D R
B A
A 1 0 /A P
C L = 2
C L = 3
W E
6
7
8
9
1 0
1 1
1 2
1 3
1 4
1 5
1 6
1 7
1 8
1 9
H IG H
t
C C D
D Q M
D Q
:D o n 't c a re
R o w A c tiv e
(A -B n a k )
R e a d (A -
B n a k )
R e a d (A -
B n a k )
W rite (A -
B n a k )
W rite (A -
B n a k )
P re c h a rg e
(A -B n a k )
* N o te1
* N o te3
* N o te2
t
R C D
t
R D L
t
C D L
R a
C a 0
C b 0
C c 0
C d 0
Q a 0
Q a 1
Q a 0
Q a 1
Q b 0
Q b 0
Q b 1
Q b 2
Q b 1
D c 0
D c 1
D c 0
D c 1
D d 0
D d 1
D d 0
D d 2
*Note : 1. To write data before burst read ends, DQM should be asserted three cycle prior to write command to
avoid bus contention.
2. Row precharge will interrupt writing. Last data input,
t
RDL
before Row precharge, will be written.
3. DQM should mask invalid input data on precharge command cycle when asserting precharge before
end of burst. Input data after Row precharge cycle will be masked internally.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| T436416A-6S | 4M X 16 SDRAM |
| T436416A-6SG | 4M X 16 SDRAM |
| T436416A-7.5S | 4M X 16 SDRAM |
| T436416A-7.5SG | 4M X 16 SDRAM |
| T436416A-7S | TERMINAL BLOCK END BARRIER IEC +OPTIONS |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| T436416A-6S | 制造商:TMT 制造商全稱:TMT 功能描述:4M X 16 SDRAM |
| T436416A-6SG | 制造商:TMT 制造商全稱:TMT 功能描述:4M X 16 SDRAM |
| T436416A-7.5S | 制造商:TMT 制造商全稱:TMT 功能描述:4M X 16 SDRAM |
| T436416A-7.5SG | 制造商:TMT 制造商全稱:TMT 功能描述:4M X 16 SDRAM |
| T436416A-7S | 制造商:TMT 制造商全稱:TMT 功能描述:4M X 16 SDRAM |
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