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參數(shù)資料
| 型號： | T555715M01-TAS |
| 廠商： | Atmel Corp. |
| 英文描述： | CONNECTOR ACCESSORY |
| 中文描述： | 連接器附件 |
| 文件頁數(shù)： | 12/30頁 |
| 文件大小： | 711K |
| 代理商： | T555715M01-TAS |
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12
T5557
4517E–RFID–02/03
Programming
When all necessary information has been received by the T5557, programming may
proceed. There is a clock delay between the end of the writing sequence and the start of
programming.
Typical programming time is 5.6 ms. This cycle includes a data verification read to grant
secure and correct programming. After programming was executed successfully, the
T5557 enters block-read mode transmitting the block just programmed (see Figure 13).
Note:
This timing and behavior is different from the e555x-family predecessors.
Error Handling
Several error conditions can be detected to ensure that only valid bits are programmed
into the EEPROM. There are two error types, which lead to two different actions.
Errors During Writing
The following detectable errors could occur during writing data into the T5557:
Wrong number of field clocks between two gaps (i.e., not a valid ‘1’ or ‘0’ pulse
stream)
Password mode is activated and the password does not match the contents of
block 7
The number of bits received in the command sequence is incorrect
Valid bit counts accepted by the T5557 are:
If any of these erroneous conditions were detected, the T5557 enters regular-read
mode, starting with block 1 of the page defined in the command sequence.
Errors Before/During
Programming
If the command sequence was received successfully, the following error could still
prevent programming:
The lock bit of the addressed block is set already
In case of a locked block, programming mode will not be entered. The T5557 reverts
to block-read mode continuously transmitting the currently addressed block.
If the command sequence is validated and the addressed block is not write protected,
the new data will be programmed into the EEPROM memory. The new state of the block
write protection bit (lock bit) will be programmed at the same time accordingly.
Each programming cycle consists of 4 consecutive steps: erase block, erase verification
(data = ‘0’), programming, write verification (corresponding data bits = ‘1’).
If a data verification error is detected after an executed data block programming, the
tag will stop modulation (modulation defeat) until a new command is transmitted.
Password write
Standard write
AOR wake up
Direct access with PWD
Direct access
Reset command
Page 0/1 regular-read
70 bits
38 bits
34 bits
38 bits
6 bits
2 bits
2 bits
(PWD = 1)
(PWD = 0)
(PWD = 1)
(PWD = 1)
(PWD = 0)
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