參數(shù)資料
型號(hào): T5743P3
廠商: Atmel Corp.
英文描述: UHF ASK/FSK Receiver
中文描述: 超高頻ASK / FSK接收器
文件頁數(shù): 10/41頁
文件大?。?/td> 681K
代理商: T5743P3
10
T5743
4569A–RKE–12/02
Figure 9.
Generation of the Basic Clock Cycle
Pin MODE can now be set in accordance with the desired clock cycle T
Clk
. T
Clk
controls
the following application relevant parameters:
Timing of the polling circuit including bit check
Timing of the analog and digital signal processing
Timing of the register programming
Frequency of the reset marker
IF filter center frequency (f
IF0
)
Most applications are dominated by two transmission frequencies: f
Send
= 315 MHz is
mainly used in USA, f
Send
= 433.92 MHz in Europe. In order to ease the usage of all T
Clk
-
dependent parameters on this electrical characteristics display three conditions for each
parameter.
Application USA (f
XTO
= 4.90625 MHz, MODE = L, T
Clk
= 2.0383 μs)
Application Europe (f
XTO
= 6.76438 MHz, MODE = H, T
Clk
= 2.0697 μs)
Other applications (T
Clk
is dependent on f
XTO
and on the logical state of Pin MODE.
The electrical characteristic is given as a function of T
Clk
).
The clock cycle of some function blocks depends on the selected baud-rate range
(BR_Range) which is defined in the OPMODE register. This clock cycle T
XClk
is defined
by the following formulas for further reference:
BR_Range = BR_Range0:
T
XClk
= 8 T
Clk
T
XClk
= 4 T
Clk
T
XClk
= 2 T
Clk
T
XClk
= 1 T
Clk
BR_Range1:
BR_Range2:
BR_Range3:
Polling Mode
According to Figure 10, the receiver stays in polling mode in a continuous cycle of three
different modes. In sleep mode the signal processing circuitry is disabled for the time
period T
Sleep
while consuming low current of I
S
= I
Soff
. During the start-up period, T
Startup
,
all signal processing circuits are enabled and settled. In the following bit-check mode,
the incoming data stream is analyzed bit by bit contra a valid transmitter signal. If no
valid signal is present, the receiver is set back to sleep mode after the period T
Bit-check
.
This period varies check by check as it is a statistical process. An average value for
T
Bit-check
is given in the electrical characteristics. During T
Startup
and T
Bit-check
the current
consumption is I
S
= I
Son
. The condition of the receiver is indicated on Pin IC_ACTIVE.
The average current consumption in polling mode is dependent on the duty cycle of the
active mode and can be calculated as:
DVCC
XTO
MODE
T
f
16
15
14
Clk
XTO
XTO
Divider
:14/:10
L : USA(:10)
H: Europe(:14)
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