參數(shù)資料
型號: T5760
廠商: Atmel Corp.
英文描述: UHF ASK/FSK Receiver
中文描述: 超高頻ASK / FSK接收器
文件頁數(shù): 8/32頁
文件大小: 765K
代理商: T5760
T5760 T5761
/
Rev. A2, 19-Oct-00
Preliminary Information
8 (32)
Sleep mode:
All circuits for signal processing are
disabled. Only XTO and Polling logic is
enabled.
Output level on Pin IC_ACTIVE => low
I
S
= I
Soff
T
Sleep
= Sleep
×
X
Sleep
×
1024
×
T
Clk
Start-up mode:
The signal processing circuits are enabled.
After the start-up time (T
Startup
) all circuits
are in stable condition and ready to receive.
Output level on Pin IC_ACTIVE => high
I
S
= I
Son
T
Startup
Bit-check mode:
The incomming data stream is analyzed. If
the timing indicates a valid transmitter
signal, the receiver is set to receiving mode.
Otherwise it is set to Sleep mode.
Output level on Pin IC_ACTIVE => high
I
S
= I
Son
T
Bit-check
Bit check
OK
Receiving mode:
The receiver is turned on permanently and
passes the data stream to the connected C.
It can be set to Sleep mode through an OFF
command via Pin DATA or POLLING/_ON.
Output level on Pin IC_ACTIVE => high
I
S
= I
Son
OFF command
Sleep:
5-bit word defined by Sleep0 to
Sleep4 in OPMODE register
Extension factor defined by
XSleep
Std
according to table 9
Basic clock cycle defined by f
XTO
and Pin MODE
X
Sleep
:
T
Clk
:
T
Startup
:
Is defined by the selected baud rate
range and T
Clk
. The baud-rate range
is defined by Baud0 and Baud1 in
the OPMODE register.
T
Bit-check:
Depends on the result of the
bit check
If the bit check is ok, T
Bit-check
depends on the number of bits to be
checked (N
Bit-check
) and on the
utilized data rate.
If the bit check fails, the average
time period for that check depends
on the selected baud-rate range and
on T
Clk
. The baud-rate range is
defined by Baud0 and Baud1 in the
OPMODE register.
NO
YES
Figure 8. Polling mode flow chart
Bit check
IC_ACTIVE
Data_out (DATA)
1/2 Bit
Start
up mode
( Number of checked Bits: 3 )
Bit check ok
1/2 Bit
1/2 Bit
1/2 Bit
1/2 Bit
1/2 Bit
Receiving mode
Dem_out
Bit
check mode
T
Start
up
T
Bit
check
Figure 9. Timing diagram for complete successful bit check
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