參數(shù)資料
型號： T66H0002A-Y
廠商： TM Technology, Inc.
英文描述： 160 output LCD Segment/Common Driver IC
中文描述： LCD段輸出160 /共同驅(qū)動器IC
文件頁數(shù)： 11/36頁
文件大?。?/td> 421K
代理商： T66H0002A-Y
TE
CH
tm
(Common mode)
SYMBOL
V
DD
Vss
T66H0002A
TM Technology Inc. reserves the right
P. 11
Publication Date: JUL. 2002
to change products or specifications without notice. Revision:A
FUNCTION
Logic system power supply pin, connected to +2.5 to +5.5 V.
Ground pin, connected to 0 V.
Bias power supply pins for LCD drive voltage
Normally use the bias voltages set by a resistor divider.
Ensure that voltages are set such that Vss < V
43
< V
12
< V
0
.
V
iL
and V
iR
(
i = 0 , 12 , 43
) must connect to an external power supply , and supply
regular voltage which is assigned by specification for each power pin.
Shift data input/output pin for bi-directional shift register
Output pin when L/R is at Vss level “L” , input pin when L/R is at V
DD
level
“H”.
When L/R = H, EIO
1
is used as input pin, it will be pulled down.
When L/R = L, EIO
1
is used as output pin, it won’t be pulled down.
Refer to “
RELATIONSHIP BETWEEN THE DISPLAY DATA AND LCD
DRIVE OUTPUT PINS
” in Functional Operations.
Shift data input/output pin for bi-directional shift register
Input pin when L/R is at Vss level “L” , output pin when L/R is at V
DD
level
“H”.
When L/R = L, EIO
2
is used as input pin, it will be pulled down.
When L/R = H, EIO
2
is used as output pin, it won’t be pulled down.
Refer to “
RELATIONSHIP BETWEEN THE DISPLAY DATA AND LCD
DRIVE OUTPUT PINS
” in Functional Operations.
Shift Clock pulse input pin for bi-directional shift register
Data is shifted at the falling edge of the clock pulse.
Input pin for selecting the shift direction of bi-directional shift register
Data is shifted from Y
160
to Y
1
when set to Vss level “L” , and data is shifted
from Y
1
to Y
160
when set to V
DD
level “H”.
Refer to “
RELATIONSHIP BETWEEN THE DISPLAY DATA AND LCD
DRIVE OUTPUT PINS
” in Functional Operations.
Control input pin for output of non-select level
The input signal is level-shifted from logic voltage level to LCD drive voltage
level, and controls the LCD drive circuit.
When set to Vss level “L”, the LCD drive output pins (Y
1
-Y
160
) are set to
level V
5
.
When set to “L”, the contents of the shift register are reset to not reading data.
When the /DISPOFF function is canceled , the driver outputs non-select level
(V
12
or V
43
), and the shift data is read at the next falling edge of the LP. At that
time , if /DISPOFF removal time does not correspond to what is shown in AC
characteristic, the shift data is not read correctly.
Table of truth value is shown in “
TRUTH TABLE
” in Functional Operations.
AC signal input pin for LCD drive waveform
The input signal is level-shifted from logic voltage level to LCD drive voltage
level, and controls the LCD drive circuit.
Normally it inputs a frame inversion signal.
The LCD drive output pins’ output voltage levels can be set using the line latch
output signal and the FR signal.
Table of truth value is shown in “
TRUTH TABLE
” in Functional Operations.
V
0L
, V
0R
V
12L
, V
12R
V
43L
, V
43R
EIO
1
EIO
2
LP
L/R
/DISPOFF
FR
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