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參數(shù)資料
| 型號： | T66H0004A1S |
| 廠商： | TM Technology, Inc. |
| 英文描述： | 80 output LCD Segment/Common Driver IC |
| 中文描述： | LCD段輸出80 /共同驅(qū)動器IC |
| 文件頁數(shù)： | 5/32頁 |
| 文件大?。?/td> | 602K |
| 代理商： | T66H0004A1S |
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T66H0004A
TM Technology Inc. reserves the right
P. 5
Publication Date: MAR. 2004
to change products or specifications without notice.
Revision:A
tm
TE
CH
BLOCK DESCRIPTION
Name
Function
COM/SEG
Clock control
Generates latch clock (LCK),shift clock(SCK) and control clock timing
according to the input of CL1,CL2 and control inputs(CS,AMS). In
common driver application mode, this block generates the shift clock
(LCK) for the common data Bi-directional shift register.
Determines the direction of segment data shift, and input data of each
Bi-directional shift register. In 4-bit segment data parallel transfer mode,
data is shifted by 4-bit unit. In common driver application mode, data is
transferred to the common data shift register directly, which disables this
block.
Controls the clock enable state of the current driver according to the
input value of enable pin (ELB or ERB). If enable input value is ”Low”,
every clock of the current driver is enabled and the clock control block
works. But if enable input is “High”, current driver is disabled and the
input data value has no effect on the output level. So power consumption
can be lowered.
Controls the output voltage level according to the input control pin (M
and DISPOFFB) (refer to PIN DESCRIPTION).
Stores output data value by shifting the input values. In 1-bit serial
interface mode application, all 80 shift clocks (SCK) are needed to store
all the display data. But in 4-bit parallel transfer mode application, only
20 clocks are needed. In common driver application mode, this block
does not work.
In segment driver application mode, the data from the 20x4-bit segment
data shift register are latched for segment driver output. In single-type
common driver application, 1-bit input data (from DL or DR pin) is
shifted and latched by the direction according to the SHL signal input. In
dual-type common application mode, 80-bit registers are divided by two
blocks and controlled independently (refer to NOTE 3).
Voltage level shifter block for high voltage part. The inputs of this block
are of logical voltage level and the outputs of this block are at high
voltage level value. These values are output to the driver.
Selects the output voltage level according to M and latched data value. If
the data value is “High” the driver output is at selected voltage level (V0
or V5), and in the reverse case the driver output value is at the
non-selected level (V12 or V43). In segment driver application mode,
non-selected output value is V2 or V3. And when in common driver
application, this value becomes V1 or V4.
COM/SEG
Data latch
control
SEG
Power down
function
SEG
Output level
selector
COM/SEG
20x4-bit
segment data
Bi-directional
shift register
SEG
80–bit data
latch/common
data
Bi-directional
shift register
COM/SEG
80-bit level
shifter
SEG
80-bit 4-level
driver
SEG
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相關(guān)代理商/技術(shù)參數(shù) |
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| T66H0004A-Q | 制造商:TMT 制造商全稱:TMT 功能描述:80 output LCD Segment/Common Driver IC |
| T66H0004A-T | 制造商:TMT 制造商全稱:TMT 功能描述:80 output LCD Segment/Common Driver IC |
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