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參數(shù)資料
| 型號(hào)： | T7295-1 |
| 廠商： | Lineage Power |
| 英文描述： | E3 Integrated Line Receiver(E3 集成線接收器) |
| 中文描述： | 綜合線接收E3展（E3展集成線接收器） |
| 文件頁(yè)數(shù)： | 11/14頁(yè) |
| 文件大?。?/td> | 321K |
| 代理商： | T7295-1 |
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Data Sheet
February 1997
T7295-1 E3 Integrated Line Receiver
11
Lucent Technologies Inc.
Electrical Characteristics
(continued)
Table 8. Logic Interface Characteristics
Timing Characteristics
Recovered Clock and Data Timing
Table 9 and Figure 9 summarize the timing relationships between the high-speed logic signals RCLK, RPDATA,
and RNDATA. RPDATA and RNDATA change on the rising edge of RCLK and are valid during the falling edge of
RCLK. A positive pulse at RIN creates a high level on RPDATA and a low level on RNDATA. A negative pulse cre-
ates a high level on RNDATA and a low level on RPDATA, and a received zero produces low levels on both RPDATA
and RNDATA.
Table 9. System Interface Timing Characteristics
All timing characteristics are measured with 10 pF loading.
5-1249(C)r.5
Figure 9. Timing Diagram for System Interface
Parameter
Symbol
Test Conditions
Min
Max
Unit
Input Voltage:
Low
High
Input Leakage
V
IL
V
IH
I
L
—
—
GND
D
0.7V
DDD
–10
20
10
–50
0.5
V
DDD
10
500
100
–5
V
V
μ
A
μ
A
μ
A
μ
A
–0.5 to V
DD
+ 0.5 V (all input pins except 2 and 17)
Pin 17, 0 V
Pin 2, V
DD
Pin 2, GND
D
Output Voltage
Low
High
Input Capacitance
Load Capacitance
V
OL
V
OH
C
I
C
L
–5.0 mA
5.0 mA
—
—
GND
D
V
DDD
– 0.5
—
—
0.4
V
DDD
10
10
V
V
pF
pF
Symbol
Parameter
Min
Typ
Max
Unit
tRCH1RCH2
tRCL2RCL1
tRDVRCL
tRCLRDX
tRCHRDV
—
Receive Clock Rise Time (10% to 90%)
Receive Clock Fall Time (90% to 10%)
Receive Data Setup Time
Receive Data Hold Time
Receive Propagation Delay
Receive Clock Duty Cycle
—
—
5.0
8.5
0.6
45
—
—
—
—
—
50
3.5
2.5
—
—
3.7
55
ns
ns
ns
ns
ns
%
tRCHRDV
tRCL2RCL1
tRCH1RCH2
tRDVRCL
tRCLRDX
RCLK
(RC)
RPDATA
OR
RNDATA
(RD)
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