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參數(shù)資料
| 型號(hào)： | T7295-6 |
| 廠商： | Lineage Power |
| 英文描述： | DS3/SONET STS-1 Integrated Line Receiver(DS3/SONET STS-1 集成線接收器) |
| 中文描述： | DS3/SONET STS - 1的集成線路接收器（DS3/SONET STS - 1的集成線接收器） |
| 文件頁(yè)數(shù)： | 3/20頁(yè) |
| 文件大?。?/td> | 416K |
| 代理商： | T7295-6 |
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Data Sheet
February 1997
T7295-6 DS3/SONET STS-1
Integrated Line Receiver
3
Lucent Technologies Inc.
Pin Information
(continued)
Table 1. Pin Descriptions
Pin
Symbol
Type
Name/Description
1
2
GND
RIN
A
—
I
Analog Ground.
Receive Input.
series with 50 k
Test Mode Control 1 and 2.
using TMC1 and TMC2. Users must tie these pins to the ground plane.
PLL Filter 1 and 2.
An external capacitor (0.1
these pins. The capacitor should be mounted as close to the pins as possible
(within 0.5 inches is recommended).
Receive Loss of Signal.
This pin is set high on loss of the data signal at the
receive input.
Receive PLL Loss of Lock.
This pin is set high on loss of PLL frequency lock.
Digital Ground for PLL Clock.
Ground lead for all circuitry running synchro-
nously with PLL clock.
Digital Ground for EXCLK.
Ground lead for all circuitry running synchronously
with EXCLK.
5 V Digital Supply (
±
10%) for PLL Clock.
nously with PLL clock.
5 V Digital Supply (
±
10%) for EXCLK.
Power for all circuitry running synchro-
nously with EXCLK.
External Reference Clock.
A valid DS3 (44.736 MHz
(51.84 MHz
±
100 ppm) clock must be provided at this input. EXCLK must be an
independent clock to help guarantee device performance for all specifications.
The duty cycle of EXCLK, referenced to V
maximum rise and fall time (10% to 90%) of 5 ns.
Receive Clock.
Recovered clock signal to the terminal equipment.
Receive Negative Data.
Negative pulse data output to the terminal equipment.
Receive Positive Data.
Positive pulse data output to the terminal equipment.
Analog receive input. This pin is internally biased at about 1.5 V in
.
Internal test modes are enabled within the device by
3, 6
TMC1—TMC2
I
4, 5
LPF1—LPF2
I
μ
F
±
20%) is connected between
7
RLOS
O
8
9
RLOL
GND
O
—
D
10
GND
C
—
11
V
DDD
—
Power for all circuitry running synchro-
12
V
DDC
—
13
EXCLK
I
±
100 ppm) or STS-1
DD
/2 levels, must be 40% to 60% with a
14
15
16
17
RCLK
RNDATA
RPDATA
ICT
O
O
O
I
In-Circuit Test Control (Active-Low).
(RCLK, RPDATA, RNDATA, RLOS, RLOL) are placed in a high-impedance state
to allow for in-circuit testing. A nominal 50 k
Receive Equalization Bypass.
A high on this pin bypasses the internal equal-
izer. A low places the equalizer in the data path.
Loss-of-Signal Threshold Control.
The voltage forced on this pin controls the
input loss-of-signal threshold. Three settings are provided by forcing GND, V
or V
DD
. This pin must be set to the desired level upon powerup and should not be
changed during operation.
5 V Analog Supply (
±
10%).
If ICT is forced low, all digital output pins
pull-up is provided on this pin.
18
REQB
I
19
LOSTHR
I
DD
/2,
20
V
DDA
—
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