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參數(shù)資料
| 型號： | T7296 |
| 廠商： | Lineage Power |
| 英文描述： | Integrated Line Transmitter(集成PCM線傳送器) |
| 中文描述： | 綜合線變送器（集成的PCM線傳送器） |
| 文件頁數(shù)： | 11/16頁 |
| 文件大小： | 396K |
| 代理商： | T7296 |
Data Sheet
February 2000
T7296 DS3/STS-1/E3
Integrated Line Transmitter
11
Lucent Technologies Inc.
Timing Characteristics
Test conditions: V
DD
= 5 V ± 5%, T
A
= –40 °C to +85 °C unless otherwise specified. All timing characteristics are
measured with 10 pF loading.
Table 9. Timing Specifications
* When the encoder is enabled, a handling delay of four and a half TCLK clock cycles for B3ZS and five and a half clock cycles for HDB3
always exists between TPDATA/TNDATA and TTIP/TRING. The handling delay is reduced to two clock cycles when the encoder is disabled.
When the decoder is enabled, a handling delay of six and a half RCLK clock cycles always exists between RPDATA/RNDATA and RPOS/
RNEG/RNRZ. The handling delay is reduced to one and a half RCLK clock cycles when the decoder is disabled.
5-3587(C)r.1
Figure 8. Transmit System-Side Timing Diagram
5-3588(C)r.1
Figure 9. Receive Line-Side Timing Diagram
Symbol
—
—
tR
tF
tTSU
tTHO
tTDY
—
tR
tF
tRSU
tRHO
tR
tF
tRDY
Parameter
Min
45
47
—
—
4.0
5.0
0.6
45
—
—
4.0
5.0
—
—
—
Typ
50
50
—
—
—
—
—
50
—
—
—
—
—
—
—
Max
55
53
4.0
4.0
—
—
14
55
4.0
4.0
—
—
4.0
4.0
4.0
Unit
%
%
ns
ns
ns
ns
ns
%
ns
ns
ns
ns
ns
ns
ns
TCLK Clock Duty Cycle (DS3/STS-1)
TCLK Clock Duty Cycle (E3)
TCLK Clock Rise Time (10% to 90%)
TCLK Clock Fall Time (90% to 10%)
Setup Time: TPDATA/TNDATA to TCLK Falling
Hold Time: TCLK Falling to TPDATA/TNDATA
Propagation Delay: TCLK Rising to TTIP/TRING*
RCLK Clock Duty Cycle
RCLK Clock Rise Time (10% to 90%)
RCLK Clock Fall Time (90% to 10%)
Setup Time: RPDATA/RNDATA to RCLK Falling
Hold Time: RCLK Falling to RPDATA/RNDATA
RCLKO Clock Rise Time (10% to 90%)
RCLKO Clock Fall Time (90% to 10%)
Propagation Delay: RCLKO Rising to RPOS/RNEG/RNRZ
TCLK
TPDATA
OR
TNDATA
TTIP
OR
TRING
tTDY
tTSU
tTHO
tR
tF
RCLK
RPDATA
OR
RNDATA
tRSU
tRHO
tF
tR
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