參數(shù)資料
型號(hào)： T7688
廠商： Lineage Power
英文描述： 5.0 V E1/CEPT Quad Line Interface(5.0 V E1/CEPT四線接口)
中文描述： 5.0V的E1/CEPT四線接口（5.0V的E1/CEPT四線接口）
文件頁(yè)數(shù)： 25/38頁(yè)
文件大?。?/td> 577K
代理商： T7688
Data Sheet
May 1998
T7688 5.0 V E1/CEPT Quad Line Interface
25
Lucent Technologies Inc.
Microprocessor Interface
(continued)
Microprocessor Interface Register Architecture
(continued)
Channel Configuration Register Overview (0110—1001)
The control bits in the channel configuration registers in Table 16 are used to select equalization, loopbacks,
AIS generation, channel alarm masking, and the channel powerdown mode for each channel (1—4). The
PWRDN[1—4], MASK[1—4], and TBS[1—4] bits are active-high. These are read/write registers.
* A numerical suffix identifies the channel number.
Channel suffix not shown in the description.
Other Registers
The bits in registers 10 and 11 must be cleared by the microprocessor after a device powerup.
The software reset bit must be cleared after powerup prior to writing any other bits in register 4.
Table 16. Channel Configuration Registers
Bits
Symbol
*
Description
Channel Configuration Registers (6—9)
The PWRDN bit powers down a channel when not used.
The MASK bit masks all interrupts for the channel.
The TBS bit enables transmission of an all 1s signal to the line interface.
The LOOPB and LOOPA bits select the channel loopback modes.
0
1
2
3,
4
5,
6,
7
PWRDN[1:4]
MASK[1:4]
TBS[1:4]
LOOPB[1:4],
LOOPA[1:4]
EQC[1:4],
EQB[1:4],
EQA[1:4]
The EQC, EQB, and EQA bits select the type of service (CEPT 75
or
CEPT 120
) and the associated transmitter cable equalization/termina-
tion impedances.
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