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參數(shù)資料
| 型號： | T7693 |
| 廠商： | Lineage Power |
| 英文描述： | 3.3 V T1/E1 Quad Line Interface( 3.3 V T1/E四線接口) |
| 中文描述： | 四3.3伏的T1/E1線路接口（3.3伏T1 /電子四線接口） |
| 文件頁數(shù)： | 28/42頁 |
| 文件大?。?/td> | 726K |
| 代理商： | T7693 |
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T7690 5.0 V T1/E1 Quad Line Interface
T7693 3.3 V T1/E1 Quad Line Interface
Data Sheet
May 1998
26
Lucent Technologies Inc.
Microprocessor Interface
(continued)
Microprocessor Interface Register Architecture
(continued)
Global Control Register Overview (0100, 0101)
The bits in the global control registers in Table 18 and Table 19 allow the microprocessor to configure the various
device functions over all the four channels. All the control bits (with the exception of LOSSTD and ICTMODE) are
active-high. These are read/write registers.
Table 18. Global Control Register (0100)
Bit
Symbol
Description
Global Control Register (4)
The GMASK bit globally masks all the channel alarms when GMASK = 1, pre-
venting all the receiver and transmitter alarms from generating an interrupt.
GMASK = 1 after a device reset.
The SWRESET provides the same function as the hardware reset. It is used
for device initialization through the microprocessor interface. The software
reset bit must be cleared after powerup prior to writing any other bits in regis-
ter 4.
The LOSSTD bit selects the conformance protocol for the DLOS receiver
alarm function.
The ICTMODE bit changes the function of the ICT pin. ICTMODE = 0 after a
device reset.
HIGHZ[1:4] A HIGHZ bit is available for each individual channel. When HIGHZ = 1, the
TTIP and TRING transmit drivers for the specified channel are placed in a
high-impedance state. HIGHZ[1:4] = 1 after a device reset.
0
GMASK
1
SWRESET
2
LOSSTD
3
ICTMODE
4—7
Table 19. Global Control Register (0101)
Bit
Symbol
Description
Global Control Register (5)
The CDR bit is used to enable and disable the clock/data recovery function.
The JAR is used to enable and disable the jitter attenuator function in the
receive path. The JAR and JAT control bits are mutually exclusive; i.e., either
JAR or the JAT control bit can be set, but not both.
The JAT is used to enable and disable the jitter attenuator function in the trans-
mit path. The JAT and JAR control bits are mutually exclusive; i.e., either JAT or
the JAR control bit should be set, but not both.
The CODE bit is used to enable and disable the B8ZS/HDB3 zero substitution
coding (decoding) in the transmit (receive) path. It is used in conjunction with
the DUAL bit and is valid only for single-rail operation.
The DUAL bit is used to select single or dual-rail mode of operation.
The ALM bit selects the transmit and receive data polarity (i.e., active-low or
active-high). The ALM and ACM bits are used together to determine the trans-
mit and receive data retiming modes.
The ACM bit selects the positive or negative edge of the receive clock
(RCLK[1:4]) for receive data retiming. The ACM and ALM bits are used together
to determine the transmit and receive data retiming modes.
The LOSSD bit selects the shutdown function for the digital loss of signal alarm
(DLOS).
0
1
CDR
JAR
2
JAT
3
CODE
4
5
DUAL
ALM
6
ACM
7
LOSSD
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