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參數(shù)資料
| 型號： | T81L0003A-AD |
| 廠商： | TM Technology, Inc. |
| 英文描述： | Reduced I/O 8-bit MCU |
| 中文描述： | 減少的I / O 8位微控制器 |
| 文件頁數(shù)： | 14/20頁 |
| 文件大?。?/td> | 113K |
| 代理商： | T81L0003A-AD |
TE
CH
tm
Watchdog Timer
T81L0003A
TM Technology, Inc. reserves the right
P. 14
to change products or specifications without notice. Revision: C
Publication Date: SEP. 2004
The watchdog timer is a 16-bit counter that is incremented once every 24 or 384 clock cycles. After an external reset the
watchdog timer is disabled and all registers are set to zeros.
!
Watchdog Timer structure
The watchdog consists of 16-bit counter
wdt
, reload register
wdtrel
, prescalers by 2 and by 16 and control logic. Where
wdtl=00h while start up.
Figure Watchdog block diagram
!
Start procedure
There are one way to start the watchdog. A programmer can start the watchdog as refreshing procedure. Once the
watchdog is started it cannot be stopped unless rst signal becomes active. When
wdt
registers enters the state 7FFCh,
asynchronous
wdts
signal will become active. The signal
wdts
sets the bit 6 in ip0 register and requests reset state. The
wdts
is cleared either by rst signal or change of the state of the
wdt
timer.
Procedure: load wdtrel value
#
set “wdt”
#
set “swdt” in 12 instruction cycles.
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| T81L0003B | 8-bit MCU |
| T81L0003B-AD | 8-bit MCU |
| T81L0003B-AK | 8-bit MCU |
| T81L0003B-BD | 8-bit MCU |
| T81L0003B-BK | 8-bit MCU |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| T81L0003A-AK | 制造商:TMT 制造商全稱:TMT 功能描述:Reduced I/O 8-bit MCU |
| T81L0003A-BD | 制造商:TMT 制造商全稱:TMT 功能描述:Reduced I/O 8-bit MCU |
| T81L0003A-BK | 制造商:TMT 制造商全稱:TMT 功能描述:Reduced I/O 8-bit MCU |
| T81L0003B | 制造商:TMT 制造商全稱:TMT 功能描述:8-bit MCU |
| T81L0003B-AD | 制造商:TMT 制造商全稱:TMT 功能描述:8-bit MCU |
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