參數(shù)資料
型號(hào)： T8536
廠商： Lineage Power
元件分類(lèi)： Codec
英文描述： Quad Programmable Codec(四通道可編程編解碼器)
中文描述： 四可編程編解碼器（四通道可編程編解碼器）
文件頁(yè)數(shù)： 47/54頁(yè)
文件大?。?/td> 1872K
代理商： T8536
Lucent Technologies Inc.
47
Preliminary Data Sheet
July 2000
T8535/T8536 Quad Programmable Codec
Software Interface
(continued)
Table 21. Control Bit Definition
(continued)
Control
Name
(Address)
PCMCTRL1
(157)
Bit
Assignment(s)
Function
7
3-state transmit PCM interface. Defaults to zero. A one forces the PCM interface
into a high-impedance state during its assigned time-slot on the PCM bus. Plac-
ing the channel in standby mode also forces a high-impedance condition on the
transmit interface.
Transmit zeros instead of data. Defaults to zero (off).
Load as zero.
Place idle-channel code on receive path. Defaults to zero (off).
Loopback receive to transmit at PCM conversion interface (
digital loopback 1
).
Resets to zero.
Loopback transmit to receive at PCM conversion interface (
analog loopback 2
).
Resets to zero.
Reserved. Must be programmed to zero. Defaults to zero.
μ
-law or A-law. A one sets A-law mode, and a zero sets
μ
-law mode. Defaults to
zero (
μ
-law).
Load as zeros.
Controls the drivers for the corresponding SLIC latches. A one enables the lead
as an output. Defaults to 0x0C (bits 2 and 3 set, the rest cleared).
Load as zeros.
SLIC data latches. If the corresponding bit in the SLICTS address is set for an
output, the device will drive the corresponding bit according to the contents of this
address. Default is zero.
Not used, ignore on read.
Reports the actual state of the SLIC leads. Anything written to this address is
ignored, and within one PCM frame (125
μ
s), the data will be overwritten.
Test location for serial interface. This location has no internal use, but merely
latches write data for the purpose of testing the serial interface.
6
5
4
3
2
1
0
SLICTS
(158)
6—7
0—5
SLICWR
(159)
6—7
0—5
SLICRD
(160)
6—7
0—5
VERIFY
(162)
0—7
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