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參數(shù)資料
| 型號(hào)： | T8538A |
| 廠商： | Lineage Power |
| 元件分類： | Codec |
| 英文描述： | Quad Programmable Codec(四通道可編程編解碼器) |
| 中文描述： | 四可編程編解碼器（四通道可編程編解碼器） |
| 文件頁數(shù)： | 37/42頁 |
| 文件大?。?/td> | 1019K |
| 代理商： | T8538A |
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Lucent Technologies Inc.
37
Advance Data Sheet
October 2000
T8538A Quad Programmable Codec
Software Interface
(continued)
Table 17. Control Bit Definition
(continued)
Control Name
(Address)
SDCTRL
(146)
Bit
Assignment(s)
7
6
3—5
Function
Load as zero.
Enable
digital loopback 3
. Defaults to zero (no loopback).
RTZ gain. Defaults to 3 (equal level point value of 3 * 0.075 = 0.225). Turn off
by writing to zero.
Transmit analog gain (XAG). Defaults to 1 (6 dB)
gain.
0—2
Bit Number
2
1
0
0
0
0
0
1
0
1
1
0
Function
(dB)
0.0
6.02
12.04
18.06
24.08
0
0
1
0
1
0
SDTSI
(147)
7
6
Load as zero.
Digital loopback, receive to transmit at the sigma-delta converters (
digital
loopback 2
). Defaults to zero (no loopback).
Digital channel feeding this analog receive channel. Defaults to channel num-
ber.
Send idle-channel code (alternating bits) to this analog receive path. Defaults
to zero (off).
Loopback from transmit to receive at the sigma-delta converters (
analog loop-
back 1
). Defaults to zero (no loopback).
Analog channel feeding this digital channel in the transmit direction. Defaults
to channel number.
Gain control for gain transfer stage in transmit direction. Defaults to 0x0400
(0 dB). This is a 12-bit multiply operation with a maximum gain of four (12 dB).
Coefficients for the transmit equalization stage. Varies frequency response
and accommodates current-sensing SLICs. Defaults to 0x000000.
Gain control for tweak gain stage in transmit direction. Defaults to 0x051a
(2.11 dB). This is a 12-bit multiply operation with a maximum gain of four
(12 dB).
Transmit direction bit offset for the FS signal. Defaults to zero. These 3 bits
can be thought of as the least significant bits (TXOFF contains the more signif-
icant bits) of a bit counter that determines the location of the first bit of the
PCM data from FS.
Load as zeros.
Transmit time-slot assignment. Defaults to (16 * channel number). Each time
slot represents 8 BCLK bits; allow for two time slots when using linear mode or
double-clock mode.
4—5
3
2
0—1
GTX2
(148—149)
ZEQTX
(150—152)
GTX1
(153—154)
0—11
0—20
0—11
TXBITOFF
(155)
5—7
0—4
0—7
TXOFF
(156)
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