147
A/T89C51CC01
4129L–CAN–08/05
Table 120.
IPH1 Register
IPH1 (S:F7h)
Interrupt High Priority Register 1
Reset Value = XXXX X000b
7
6
5
4
3
2
1
0
-
-
-
-
POVRH
PADCH
PCANH
Bit
Number
Bit
Mnemonic
Description
7
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
6
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
5
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
3
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
2
POVRH
Timer overrun Interrupt Priority Level Most Significant bit
POVRH POVRL Priority level
0
0
Lowest
0
1
1
0
1
1
Highest
1
PADCH
ADC Interrupt Priority Level Most Significant bit
PADCH PADCL Priority level
0
0
Lowest
0
1
1
0
1
1
Highest
0
PCANH
CAN Interrupt Priority Level Most Significant bit
PCANH PCANLPriority level
0
0
Lowest
0
1
1
0
1
1
Highest
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