參數(shù)資料
型號: T89C51RD2-RLTCL
廠商: ATMEL CORP
元件分類: 微控制器/微處理器
英文描述: 0 to 40 MHz Flash Programmable 8-bit Microcontroller
中文描述: 8-BIT, FLASH, 25 MHz, MICROCONTROLLER, PQFP44
封裝: VQFP-44
文件頁數(shù): 42/104頁
文件大?。?/td> 798K
代理商: T89C51RD2-RLTCL
42
T89C51RD2
4243G
8051
05/03
Power Management
Two power reduction modes are implemented in the T89C51RD2: the Idle mode and the
Power-down mode. These modes are detailed in the following sections. In addition to
these power reduction modes, the clocks of the core and peripherals can be dynamically
divided by 2 using the X2 mode detailed in Section
X2 Feature
.
Reset
In order to start-up (cold reset) or to restart (warm reset) properly the microcontroller, an
high level has to be applied on the RST pin. A bad level leads to a wrong initialization of
the internal registers like SFRs, Program Counter
and to unpredictable behavior of
the microcontroller. A proper device reset initializes the T89C51RD2 and vectors the
CPU to address 0000h. RST input has a pull-down resistor allowing power-on reset by
simply connecting an external capacitor to V
DD
as shown in Figure 17. A warm reset can
be applied either directly on the RST pin or indirectly by an internal reset source such as
the watchdog timer. Resistor value and input characteristics are discussed in the Sec-
tion
DC Characteristics
of the T89C51RD2 datasheet.
Figure 17.
Reset Circuitry and Power-On Reset
Cold Reset
2 conditions are required before enabling a CPU start-up:
V
DD
must reach the specified V
DD
range
The level on X1 input pin must be outside the specification (V
IH
, V
IL
)
If one of these 2 conditions are not met, the microcontroller does not start correctly and
can execute an instruction fetch from anywhere in the program space. An active level
applied on the RST pin must be maintained till both of the above conditions are met. A
reset is active when the level V
IH1
is reached and when the pulse width covers the
period of time where V
DD
and the oscillator are not stabilized. 2 parameters have to be
taken into account to determine the reset pulse width:
V
DD
rise time,
Oscillator startup time.
To determine the capacitor value to implement, the highest value of these 2 parameters
has to be chosen. Table 26 gives some capacitor values examples for a minimum R
RST
of 50 K
and different oscillator startup and V
DD
rise times.
R
R
RST
VSS
To CPU Core
and Peripherals
RST
VDD
+
Power-on Reset
RST input circuitry
P
VDD
From Internal
Reset Source
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