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參數(shù)資料
| 型號： | T89C51RD2-SLRIM |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 0 to 40 MHz Flash Programmable 8-bit Microcontroller |
| 中文描述： | 8-BIT, FLASH, 40 MHz, MICROCONTROLLER, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數(shù)： | 77/104頁 |
| 文件大?。?/td> | 798K |
| 代理商： | T89C51RD2-SLRIM |
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77
T89C51RD2
4243G
–
8051
–
05/03
1. In Page Load Mode the current byte is loaded on ALE rising edge.
2. After a power up all external test mode to program or to erase the Flash are locked to avoid any untimely programming or
erasure.
After each programming or erasure test mode, it
’
s advised to lock this feature (test mode PELCK).
To validate the test mode mode PEULCK the following sequence has to be applied:Test Mode PEULCK with ALE = 1.
Pulse on ALE (min width=25clk) with P0=55 (P0 latched on ALE rising edge)
Pulse on ALE (min width=25clk) with P0=AA (P0 latched on ALE rising edge)
3. The highest security bit (bit 7) is used to secure the 7 lowest bit erasure. The only way to erase this bit is to erase the whole
Flash memory.
Procedure to program security bits (After array programming):
- program bit7 to 0, program all other bits ( 1 = erased, 0 = programmed).
- test mode PGMS (din = HSB).
Procedure to erase security byte:
- test mode CERR: erase all array included HSB.
- program hardware security byte to FF: test mode PGMS (din = FF).
Mode
Name
Mode
P1[7..0]
P2[5..0]
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
PELCK
Program or Erase Lock.
Disable the Erasure or Programming access
xx
xx
x
x
x
1
x
x
PEULCK
Program or Erase UnLock.
Enable the Erasure or Programming access
xx
xx
x
x
x
0
x
x
PGMC
Write Code Data (byte)
or write Page
Always precedeed by PGML
A7-A0
A13-A8
1
x
x
0
A14
A15
PGML
Memory Page Load
(up to 128 bytes)
A7-A0
A13-A8
1
x
x
0
A14
A15
PGMV
Read Code Data (byte)
A7-A0
A13-A8
1
x
x
1
A14
A15
VSB
Read Security Byte (=HSB)
xx
xx
1
x
x
1
x
x
PGMS
Write lock Byte (Note 4)
(security byte = HSB)
xx
xx
1
x
x
0
x
x
CERR
Chip Erase User + XAF
xx
xx
1
x
x
0
x
x
PGXC
Write Byte or Page Extra Memory (XAF)
Always precedeed by PGXL
A7-A0
(0-7F)
xx
1
x
x
0
x
x
PGXL
Memory Page Load XAF
(up to 128 bytes)
A7-A0
(0-7F)
xx
1
x
x
1
x
x
TMS
Read Signature bytes
30h (Manufacturer code)
31h (Device ID #1)
60h (Device ID #2)
61h (Device ID #3)
30h
31h
60h
61h
x
x
x
x
1
x
x
RXAF
Read Extra Memory
(XAF)
Addr
(0-7F)
00
1
x
x
0
x
x
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| T89C51RD2-SLSCL | 0 to 40 MHz Flash Programmable 8-bit Microcontroller |
| T89C51RD2-SLSCM | 0 to 40 MHz Flash Programmable 8-bit Microcontroller |
| T89C51RD2-SLSIL | 0 to 40 MHz Flash Programmable 8-bit Microcontroller |
| T89C51RD2-SLSIM | 0 to 40 MHz Flash Programmable 8-bit Microcontroller |
| T89C51RD2-SLUCM | 0 to 40 MHz Flash Programmable 8-bit Microcontroller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| T89C51RD2-SLRI-M | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:0 to 40MHz Flash Programmable 8-bit Microcontroller |
| T89C51RD2-SLSCL | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:0 to 40 MHz Flash Programmable 8-bit Microcontroller |
| T89C51RD2-SLSC-L | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:0 to 40MHz Flash Programmable 8-bit Microcontroller |
| T89C51RD2-SLSCM | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:0 to 40 MHz Flash Programmable 8-bit Microcontroller |
| T89C51RD2-SLSC-M | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:0 to 40MHz Flash Programmable 8-bit Microcontroller |
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