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參數(shù)資料
| 型號： | T8A10-800H-TR |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 8A TRIACS |
| 中文描述： | 8A條雙向可控硅 |
| 文件頁數(shù)： | 6/10頁 |
| 文件大?。?/td> | 47K |
| 代理商： | T8A10-800H-TR |
BTA/BTB08 and T8 Series
6/10
Fig. 6:
current
tp < 10ms, and corresponding value of I t.
Non-repetitive surge peak on-state
for
a
sinusoidal
pulse
with
width
Fig. 7:
Relative variation of gate trigger current,
holding current and latching current versus
junction temperature (typical values).
Fig. 8-1:
Relative variation of critical rate of
decrease of main current versus (dV/dt)c (typical
values). Snubberless & Logic Level Types
Fig. 8-2:
Relative variation of critical rate of
decrease of main current versus (dV/dt)c (typical
values). Standard Types
Fig. 9:
Relative variation of critical rate of
decrease
of
main
current
temperature.
versus
junction
Fig. 10:
DPAK and D
2
PAK Thermal resistance
junction to ambient versus copper surface under
tab (printed circuit board FR4, copper thickness:
35
μ
m).
0.01
0.10
1.00
10.00
10
100
1000
ITSM (A),
I t
(A s)
Tj initial=25
°
C
ITSM
I t
dI/dt limitation:
50A/
s
tp (ms)
-40
-20
0
20
40
60
80
100
120
140
0.0
0.5
1.0
1.5
2.0
2.5
IGT,IH,IL[Tj]/ IGT,IH,IL [Tj=25
°
C]
IGT
IH &IL
Tj(
°
C)
0.1
1.0
10.0
100.0
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
(dI/dt)c [(dV/dt)c] / Specified (dI/dt)c
T835/CW/BW
TW
T810/SW
(dV/dt)c (V/
μ
s)
0.1
1.0
10.0
100.0
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
(dI/dt)c [(dV/dt)c] / Specified (dI/dt)c
C
B
(dV/dt)c (V/
μ
s)
0
25
50
75
100
125
0
1
2
3
4
5
6
(dI/dt)c [Tj] / (dI/dt)c [Tj specified]
Tj(
°
C)
0
4
8
12
16
20
24
28
32
36
40
0
10
20
30
40
50
60
70
80
90
100
Rth(j-a) (
°
C/W)
DPAK
D PAK
S(cm )
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| T8A35-600H | 8A TRIACS |
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