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| 型號(hào)： | T9000 |
| 廠商： | Lineage Power |
| 英文描述： | ISDN Network Termination Node (NTN) Device(ISDN網(wǎng)絡(luò)終端節(jié)點(diǎn)器件) |
| 中文描述： | ISDN網(wǎng)絡(luò)終端節(jié)點(diǎn)（新界西）設(shè)備（ISDN網(wǎng)網(wǎng)絡(luò)終端節(jié)點(diǎn)器件） |
| 文件頁(yè)數(shù)： | 56/126頁(yè) |
| 文件大?。?/td> | 1523K |
| 代理商： | T9000 |
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56
Lucent Technologies Inc.
Advance Data Sheet
April 2000
ISDN Network Termination Node (NTN) Device
T9000
9 HDLC with FIFO Module
(continued)
9.3 HDLC Receiver
(continued)
9.3.1 HDLC Receiver Initialization
(continued)
Up to 16 status bytes can be stored in the receiver
FIFO at a given time. Once this condition is reached, it
is indicated by assertion of the HIR[RSTF] interrupt
register bit and the FIFO is considered full. In the worst
case, the microcontroller has approximately 2 ms from
the time HIR[RSTF] is asserted to read data from the
FIFO and avoid overrun errors (an overrun error is indi-
cated by assertion of the HIR[ROVR] interrupt bit).
When a status word with its EOF bit set is loaded into
the FIFO, interrupt bit HIR[REOF] is set. Similarly,
when a status word with its ABRT bit set is loaded into
the FIFO, interrupt bit HIR[RABT] is set.
When the receive FIFO is filled at or above the level
programmed in register HRTH, an interrupt is asserted
by enabling the bit HIR[RTHR]. The interrupt should
clear when the interrupt status register is read, and
should not be asserted again until the receive FIFO is
emptied to the point that more spaces remain in the
FIFO than the value programmed in the HRTH register,
and then enough bytes are received to again cause the
delay FIFO fill level to reach the HRTH register value.
9.3.1.1 Overrun Condition
An overrun condition occurs when the receiver is
unable to download a processed byte into the FIFO
because the FIFO is full or contains 16 status words.
Interrupt bit HIR[ROVR] is set when an overrun occurs.
If the overrun condition occurs during the reception of a
packet with a matching address field, the current frame
will be closed and its status word’s OVR bit will be set.
The remainder of the frame will be dropped even if the
overrun condition has been removed. The receiver
must be reinitialized after the overrun condition, before
new packets can be properly received.
9.4 Address Recognition
A very flexible address comparison scheme is imple-
mented in the NTN device. Eight registers are used for
storing SAPI or TEI patterns for comparison with the
incoming address. The registers are grouped logically
into the pairs HSM0/HTM0, HSM1/HTM1, HSM2/
HTM2, HSM3/HTM3 to define a total of four DLCI (data
link connection identifier) address matching patterns. If
HSMOD and HTMOD are programmed for address
matching, only frames with an address field matching
one of the programmed address values (or special
addresses) are transferred to the receive FIFO. All oth-
ers are ignored. If an address match occurs, the
address field is also loaded into the HDLC receive
FIFO.
The address modifier registers, HSMOD and HTMOD,
are used to control the address recognition modes and
can be used to extend the DLCIs defined in the four
HSMx/HTMx register pairs. Figure 12 shows an exam-
ple of this for the SAPI0/TEI0 pair (i.e., bits
SAPI0M[1:0] and TEI0M[1:0] in HSMOD and HTMOD,
respectively).
Consider the default setting of TEI0M = 00 and
SAPI0M = 00 on powerup. In this case, TEIM0 = 00
causes rejection of all packets for a given DLCI pair,
independent of the state of SAPI0M. This means that
on powerup, the HDLC receiver is disabled and will not
receive any packets. Now consider the effect of setting
TEI0M to the other three possible values while leaving
SAPI0M set to 00.
Setting TEI0M = 01 enables the recognition of the
DLCI0 address programmed in the HSM0/HTM0 pair.
Setting TEI0M = 10 extends the definition of DLCI0 to
include the broadcast TEI value, 127. Setting TEI0M =
11 extends the definition of DLCI0 to include all TEI val-
ues.
In a similar way, setting SAPI0M to the values 01, 10,
or 11 will extend the existing definition of DLCI0 to
include SAPI0 = 0, SAPI = 63, or all SAPI values,
respectively. Note, then, that when SAPI0M/TEI0M =
1111, any packet more than 2 bytes in length (4 bytes if
HRCF[DROPCRC] = 1) will be downloaded to the
receiver FIFO, regardless of its address. This effec-
tively disables address recognition for all four DLCI
pairs, since the values programmed into the other three
pairs become irrelevant in this case.
One further level of address recognition control is avail-
able via the HSCR register, which provides a means for
enabling/disabling comparison of the command
response (C/R) bit for each SAPI. When
HSCR[SxCRE] = 0, no comparison is done on the C/R
bit of the SAPI defined by HSMx register. When
HSCR[SXCRE] = 1, the C/R bit is included in compari-
son. However, for extended SAPI values of 0 or 63
(HSMOD[SAPIxM] = 01 or = 10), no comparison is ever
done on the C/R bit.
In the transmit direction, no automatic address inser-
tion is performed.
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