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參數(shù)資料
| 型號(hào)： | TA1318AFG |
| 廠商： | Toshiba Corporation |
| 英文描述： | Zener Diode; Application: Low noise; Pd (mW): 250; Vz (V): 4.0 to 4.4; Condition Iz at Vz (mA): 0.5; C (pF) max: -; Condition VR at C (V):   ESD (kV) min: -; Package: DO-35 |
| 中文描述： | 同步處理器，頻率計(jì)數(shù)器集成電路電視分量信號(hào) |
| 文件頁(yè)數(shù)： | 17/42頁(yè) |
| 文件大小： | 370K |
| 代理商： | TA1318AFG |
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TA1318AFG
2006-02-27
17
Data Transmit Format 1
Data Transmit Format 2
Data Receive Format
At the moment of the first acknowledge, the master transmitter becomes a master receiver and the slave
transmitter. This acknowledge is still generated by this slave.
The Stop condition is generated by the master.
(
*
important) The data read from THIS IC should always be completed in whole two words, not one word,
otherwise the IICBUS may cause error.
Optional Data Transmit Format: Automatic Increment Mode
In this transmission method, data is set on automatically incremented sub-address from the specified
sub-address.
I
2
C BUS Conditions
Characteristics
Symbol
Min
Typ.
Max
Unit
Low level input voltage
V
IL
V
IH
V
OL1
0
1.5
V
High level input voltage
3.0
Vcc
V
Low level output voltage at 3 mA sink current
0
0.4
V
Input current each I/O pin with an input voltage
between 0.1 VDD and 0.9 VDD
I
i
10
10
μ
A
Capacitance for each I/O pin
C
i
f
SCL
t
HD;STA
t
LOW
t
HIGH
t
SU;STA
t
HD;DAT
t
SU;DAT
t
SU;STO
t
BUF
10
pF
SCL clock frequency
0
100
kHz
Hold time START condition
4.0
μ
s
Low period of SCL clock
4.7
μ
s
High period of SCL clock
4.0
μ
s
Set-up time for a repeated START condition
4.7
μ
s
Data hold time
280
ns
Data set-up time
250
ns
Set-up time for STOP condition
4.0
μ
s
Bus free time between a STOP and START condition
4.7
μ
s
S
Slave address
7 bit
0 A
Transmit data
8 bit
A
Sub address
8 bit
A P
MSB
S: Start condition
MSB
A: Acknowledge
MSB
P: Stop condition
S
Slave address
0 A
Transmit data
A
Sub address
A
Transmit data n
A
Sub address
A P
S
Slave address
7 bit
1 A
Received data 2
A
Received data 1
8 bit
A P
MSB
MSB
S
Slave address
7 bit
A
Transmit data 2
8 bit
Transmit data 1
8 bit
A P
MSB
MSB
0
Sub address
7 bit
MSB
A 1
MSB
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