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| 型號(hào)： | TA2069AF |
| 元件分類： | 音頻控制 |
| 英文描述： | 2 CHANNEL(S), TONE CONTROL CIRCUIT, PDSO24 |
| 封裝： | 0.300 INCH, 1 MM PITCH, PLASTIC, SSOP-24 |
| 文件頁(yè)數(shù)： | 2/14頁(yè) |
| 文件大?。?/td> | 298K |
| 代理商： | TA2069AF |
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TDA9885_TDA9886_3
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 16 December 2008
10 of 56
NXP Semiconductors
TDA9885; TDA9886
I2C-bus controlled multistandard alignment-free IF-PLL demodulators
8.6 AFC and digital acquisition help
Each relaxation oscillator of the VIF-PLL and FM-PLL demodulator has a wide frequency
range. To prevent false locking of the PLLs and with respect to the catching range, the
digital acquisition help provides an individual control, until the frequency of the VCO is
within the preselected standard dependent lock-in window of the PLL.
The in-window and out-window control at the FM PLL is additionally used to mute the
audio stage (if auto mute is selected via the I2C-bus).
The working principle of the digital acquisition help is as follows. The PLL VCO output is
connected to a down counter which has a predened start value (standard dependent).
The VCO frequency clocks the down counter for a xed gate time. Thereafter, the down
counter stop value is analyzed. In case the stop value is higher (lower) than the expected
value range, the VCO frequency is lower (higher) than the wanted lock-in window
frequency range. A positive (negative) control current is injected into the PLL loop lter
and consequently the VCO frequency is increased (decreased) and a new counting cycle
starts.
The gate time as well as the control logic of the acquisition help circuit is dependent on the
precision of the reference signal at pin REF. Operation as a crystal oscillator is possible as
well as connecting this input via a serial capacitor to an external reference frequency, e.g.
the tuning system oscillator.
The AFC signal is derived from the corresponding down counter stop value after a
counting cycle. The last four bits are latched and can be read out via the I2C-bus
(see Table 8). Also the digital-to-analog converted value is given as current at pin AFC.
8.7 Video demodulator and amplier
The video demodulator is realized by a multiplier which is designed for low distortion and
large bandwidth. The VIF signal is multiplied with the ‘in phase’ signal of the VIF-PLL
VCO.
The demodulator output signal is fed into the video preamplier via a level shift stage with
integrated low-pass lter to achieve carrier harmonics attenuation.
The output signal of the preamplier is fed to the VIF-AGC detector (see Section 8.3) and
in the sound trap mode also fed internally to the integrated sound carrier trap
(see Section 8.8). The differential trap output signal is converted to a single-ended signal
and amplied by the following post-amplier. The video output level at pin CVBS is
2 V (p-p).
In the trap bypass mode the output signal of the preamplier is fed directly through the
post-amplier to pin CVBS. The output video level is 1.1 V (p-p) for using an external
sound trap with 10 % overall loss.
Noise clipping is provided in both cases.
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