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參數(shù)資料
| 型號： | TA235 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | TECHNICAL ARTICLE |
| 中文描述： | 技術(shù)文章 |
| 文件頁數(shù)： | 2/6頁 |
| 文件大小： | 35K |
| 代理商： | TA235 |
TA 235
2/6
Figure 2. Firmware Hub Read Protocol
Figure 3. Firmware Hub Write Protocol
AI03437
CLK
FWH4
FWH0-FWH3
Number of
clock cycles
START
IDSEL
ADDR
MSIZE
TAR
SYNC
DATA
TAR
1
1
7
1
2
3
2
2
AI03441
CLK
FWH4
FWH0-FWH3
Number of
clock cycles
START
IDSEL
ADDR
MSIZE
DATA
TAR
SYNC
TAR
1
1
7
1
2
2
1
2
Firmware Hub Interface
The FWH Interface features:
I
a five Signal Communication Interface (FWH0-
FWH4) to support the Read and Write
operations,
I
five General Purpose Inputs (FGPI0-FGPI4) for
platform design flexibility,
I
four Identification Inputs (ID0-ID3) to address
up to 16 different memory devices,
I
a Register Based Block Locking and a
Hardware Block Protection for firmware
security.
It has an Input Clock (CLK) synchronized with the
33MHz PCI clock and a 3.3V Input/Output bus.
Figure 1 shows the pin description for FWH
interface mode.
There are two different protection modes designed
for the FWH interface. The hardware protection
has the Top Block Lock (TBL) that prevents the
Top Block from being changed, and the Write
Protect (WP
)
that prevents all the other blocks
from being changed.
Figure 4. Address/Address Multiplexed
Interface Configuration
AI03796
11
G
DQ0-
DQ7
VCC
M50FW040
RC
VSS
8
IC
RP
RB
W
A0-A10
VPP
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