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參數(shù)資料
| 型號(hào)： | TAFE1040PFB |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 3 V, 10-BIT 42 MSPS, AREA CCD ANALOG FRONT-END |
| 中文描述： | 3伏，10位42 MSPS的，面陣CCD模擬前端 |
| 文件頁(yè)數(shù)： | 3/4頁(yè) |
| 文件大?。?/td> | 53K |
| 代理商： | TAFE1040PFB |
TAFE1040
3 V, 10-BIT 42 MSPS, AREA CCD ANALOG FRONT-END
SLVS284 – FEBRUARY 2000
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
ADCCLK
NO.
25
I
ADC clock input
DGND
5
Digital ground
AGND1
44
Analog ground for internal CDS circuits
AGND2
4
Analog ground for internal PGA circuits
AGND3
20
Analog ground for internal DAC circuits
AGND4
32
Analog ground for internal ADC circuits
AGND5
37
Analog ground for internal REF circuits
AVDD1
43
Analog supply voltage for internal CDS circuits, 3 V
AVDD2
3
Analog supply voltage for internal PGA circuits, 3 V
AVDD3
19
Analog supply voltage for internal DAC circuits, 3 V
AVDD4
33
Analog supply voltage for internal ADC circuits, 3 V
AVDD5
41
Analog supply voltage for internal ADC circuits, 3 V
BLKG
36
I
Control input. The CDS operation is disabled when the BLKG is pulled low.
CLAMP
47
I
CCD signal clamp control input
CLREF
48
O
Clamp reference voltage output
CS
28
I
Chip select. A logic low on this input enables the TLV097A.
DACO1
21
O
Digital-to-analog converter output1
DACO2
22
O
Digital-to-analog converter output2
DIGND
18
Digital interface circuit ground
DIN
1
I
Input signal from CCD
DIVDD
17
Digital interface circuit supply voltage, 1.8 V–4.4 V
DVDD
6
Digital supply voltage, 3 V
D0–D9
7–16
O
10-Bit 3-state ADC output data or offset DACs test data
OBCLP
31
I
Optical black level and offset calibration control input. Active low
OE
24
I
Output data enable. Active low
PIN
2
I
Input signal from CCD
RBD
38
O
Internal bandgap reference for external decoupling
RESET
29
I
Hardware reset input, active low. This signal forces a reset of all internal registers.
RMD
39
O
REF– output for external decoupling
RPD
40
O
Ref+ output for external decoupling
SCKP
23
I
This pin selects the polarity of SCLK. 0 – active low (high when SCLK is not running), 1 – active high (low when
SCLK is not running)
SCLK
26
I
Serial clock input. This clock synchronizes the serial data transfer.
SDIN
27
I
Serial data input to configure the internal registers
SR
45
I
CCD reference level sample clock input
STDY
30
I
Hardware power-down control input, active low
SV
46
I
CCD signal level sample clock input
TPM
34
O
Mux’ed test output: PGA noninverting output or inverted PGA clock
TPP
35
O
Mux’ed test output: PGA inverting output or inverted CDS clock
VSS
42
Silicon substrate, normally connected to analog ground
P
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