- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄98158 > TAS3001CPWG4 (TEXAS INSTRUMENTS INC) 2 CHANNEL(S), TONE CONTROL CIRCUIT, PDSO28 PDF資料下載
參數(shù)資料
| 型號： | TAS3001CPWG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 音頻控制 |
| 英文描述： | 2 CHANNEL(S), TONE CONTROL CIRCUIT, PDSO28 |
| 封裝： | GREEN, PLASTIC, TSSOP-28 |
| 文件頁數(shù)： | 6/55頁 |
| 文件大?。?/td> | 432K |
| 代理商： | TAS3001CPWG4 |
第1頁第2頁第3頁第4頁第5頁當前第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁
21
2 Audio Data Formats
2.1
Serial Audio Interface
The TAS3001 operates in digital audio slave mode only. The TAS3001 supports three serial audio data formats: I2S,
left-justified, and right-justified. Data word lengths of 16, 18, and 20 bits are supported.
Data is input into SDIN1 and SDIN2 under the influence of the master clock (MCLK), left/right clock (LRCLK), and
shift clock (SCLK) inputs.
Data is output on the SDOUT pin under the influence of the master clock (MCLK) input plus the left/right clock
(LRCLKOUT) and shift clock (SCLKOUT) outputs. LRCLKOUT and SCLKOUT are generated from the MCLK input
(usually at 256
× fs). Typically these are routed on the PCB to LRCLK (as the input fs sample clock) and SCLK (as
the input 64
× fs bit clock).
The TAS3001 device is compatible with 10 different serial interfaces. Available interface options are I2S,
right-justified, and left-justified. Table 21 and Table 22 indicate how the 10 options are selected using the I2C bus
and the main control register (MCR, I2C address 01h). All serial interface options at either 16, 18, or 20 bits operate
with SCLK at 64
× fs. The 16-bit mode, left-justified, can operate at 32 × fs or 64 × fs.
Table 21. Serial Interface Input Options
MODE
MCR BIT 6
SC
MCR BITS 32
F(1,0)
MCR BITS 10
W(1,0)
SERIAL INTERFACE
SDIN1, SDIN2
0
00
16-bit, left-justified, 32
× fs
1
00
16-bit, left-justified, 64
× fs
2
1
01
00
16-bit, right-justified, 64
× fs
3
1
10
00
16-bit, I2S, 64
× fs
4
1
00
01
18-bit, left-justified, 64
× fs
5
1
01
18-bit, right-justified, 64
× fs
6
1
10
01
18-bit, I2S, 64
× fs
7
1
00
10
20-bit, left-justified, 64
× fs
8
1
01
10
20-bit, right-justified, 64
× fs
9
1
10
20-bit, I2S, 64
× fs
Table 22. Serial Interface Output Options
MODE
MCR BIT 6
SC
MCR BITS 54
E(1,0)
MCR BITS 10
W(1,0)
SERIAL INTERFACE
SDOUT
0
00
16-bit, left-justified, 32
× fs
1
00
16-bit, left-justified, 64
× fs
2
1
01
00
16-bit, right-justified, 64
× fs
3
1
10
00
16-bit, I2S, 64
× fs
4
1
00
01
18-bit, left-justified, 64
× fs
5
1
01
18-bit, right-justified, 64
× fs
6
1
10
01
18-bit, I2S, 64
× fs
7
1
00
10
20-bit, left-justified, 64
× fs
8
1
01
10
20-bit, right-justified, 64
× fs
9
1
10
20-bit, I2S, 64
× fs
Figure 21 through Figure 24 illustrate the relationship between the SCLK, LRCLK, and the serial data input and
output protocol options.
相關PDF資料 |
PDF描述 |
|---|---|
| TAS3001CPW | 2 CHANNEL(S), TONE CONTROL CIRCUIT, PDSO28 |
| TAS3002 | SPECIALTY CONSUMER CIRCUIT, PQFP48 |
| TAS3004PFB | SPECIALTY CONSUMER CIRCUIT, PQFP48 |
| TAS3004PFBR | SPECIALTY CONSUMER CIRCUIT, PQFP48 |
| TAS3004PFBG4 | SPECIALTY CONSUMER CIRCUIT, PQFP48 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| TAS3001CPWR | 功能描述:音頻 DSP Stero Audio Digital Equalizer RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風格: 封裝 / 箱體: 封裝:Tube |
| TAS3001CPWRG4 | 功能描述:音頻 DSP Stero Audio Digital Equalizer RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風格: 封裝 / 箱體: 封裝:Tube |
| TAS3001EVM | 制造商:Texas Instruments 功能描述:TAS3001 EVALUATION BOARD - Bulk |
| TAS3001IN WAF | 制造商:Texas Instruments 功能描述: |
| TAS3002 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Digital Audio Processor With Codec |
發(fā)布緊急采購，3分鐘左右您將得到回復。