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參數(shù)資料
| 型號： | TAS3001CPWRG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 音頻控制 |
| 英文描述： | 2 CHANNEL(S), TONE CONTROL CIRCUIT, PDSO28 |
| 封裝： | GREEN, PLASTIC, TSSOP-28 |
| 文件頁數(shù)： | 5/55頁 |
| 文件大小： | 432K |
| 代理商： | TAS3001CPWRG4 |
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18
1.12 Pin Functions
TERMINAL
I/O
DESCRIPTION
NAME
NO.
I/O
DESCRIPTION
AVDD_PLL
13
I
Analog power supply for the PLL
AVSS_PLL
12
I
Analog ground for the PLL
CAP_PLL
14
I
C1 = 1500 pF // R1 = 27
+ C2 = 0.068 F (recommended)
CS1
28
I
I2C address bit A0; low = 0, high = 1
CS2
1
I
I2C address bit A1; low = 0, high = 1
DVDD
3
I
Digital power supply
DVSS
2
I
Digital ground
LRCLK
10
I
I2S left/right clock sampling frequency (fs)
LRCLKOUT
23
O
LRCLK generated from input MCLK (usually 256 fs) normally routed on PCB to pin 10
(LRCLK) as input fs sample clock.
MCLK
9
I
Master clock (256 x fs)
NC
17, 18, 2022,
25, 26
Reserved No connection for normal operation
POWERDOWN
16
I
Powerdown input
RESET
19
I
Reset, high = normal operation, low = reinitialize the device
RESERVED
15, 27
Reserved digital ground for normal operation
SCL
5
I/O
Slave serial I2C clock
SCLK
11
I
Shift clock (bit clock)
SCLKOUT
24
O
SCLK generated from input MCLK (usually 256 fs) normally routed on PCB to pin 11 (SCLK)
as input 64 fs bit clock.
SDA
4
I/O
Slave serial I2C data
SDIN1
6
I
Serial audio data input one
SDIN2
7
I
Serial audio data input two
SDOUT
8
O
Serial audio data output
NOTE: Reset and other control functions require MCLK to be running. The system reset operation is a synchronous operation and requires a
minimum of four MCLK cycles to reset the device.
1.13 Ordering Information
TA
PACKAGE
TA
SMALL OUTLINE (PW)
0
°C to 70°C
TAS3001CPW
1.14 Power Supply
Digital supply voltage—DVDD, DVSS of 3.3 V
Analog supply voltage—AVDDPLL, AVSSPLL of 3.3 V
NOTE: AVDD and AVSS for the PLL are derived from the digital supply and digital ground.
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