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| 型號(hào)： | TAS3218IPZP |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類(lèi)： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP100 |
| 封裝： | GREEN, PLASTIC, TQFP-100 |
| 文件頁(yè)數(shù)： | 42/79頁(yè) |
| 文件大?。?/td> | 1263K |
| 代理商： | TAS3218IPZP |
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SPDIF INTERFACE SIGNALS TIMING CHARACTERISTICS
I
2C INTERFACE AND I/O CHARACTERISTICS OF THE SDA AND SCL BUS LINES FOR
www.ti.com ....................................................................................................................................................................................................... SLES235 – JULY 2008
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Fs
Encoded data sampling rate
32
48
kHz
Rspdif
SPDIF signal bitrate
128 Fs
MHz
UI
Unit interval
1/Rspdif
ns
TLO/THI
Low/high periods
1 UI
3 UI
ns
VOH
High-level output voltage
3.3-V TTL, IOH = 4 mA
2.4
V
VOL
Low-level output voltage
3.3-V TTL, IOL = 4 mA
0.5
V
STANDARD- AND FAST-MODE I
2C BUS DEVICES
See Figure 38
PARAMETER
STANDARD MODE
FAST MODE
UNIT
MIN
MAX
MIN
MAX
fSCL
SCL clock frequency
0
100
0
400(1)
kHz
Hold time (repeated) START condition. After this period,
tHD;STA
4
0.6
s
the first clock pulse is generated.
tLOW
LOW period of the SCL clock
4.7
1.3
s
tHIGH
HIGH period of the SCL clock
4
0.6
s
tsu;STA
Set-up time for a repeated START condition
4.7
0.6
s
tsu;DAT
Data set-up time
250
100(2)
ns
tr
Rise time of both SDA and SCL signals
1000
20 + 0.1 Cb
(3)
300
ns
tf
Fall time of both SDA and SCL signals
300
20 + 0.1 Cb
(3)
300
ns
tsu;STO
Set-up time for STOP condition
4
0.6
s
tBUF
Bus free time between a STOP and START condition
4.7
1.3
s
Cb
Capacitive load for each bus line
400
pF
Noise margin at the LOW level for each connected device
VnL
0.1 VDD
V
(including hysteresis)
Noise margin at the HIGH level for each connected device
VnH
0.2 VDD
V
(including hysteresis)
Vhys
Hysteresis of Schmitt trigger inputs
0.05 VDD
V
Pulse width of spikes which must be suppressed by the
tSP
0
50
ns
input filter
Input current each I/O pin with an input voltage between
Ii
10
10(4)
A
0.1 VDD and 0.9 VDD max
Ci
Capacitance for each I/O pin
10
pF
Output fall time from VIHmin to VILmax with a bus
tof
250(5)
7 + 0.1 Cb
(3)
250(5)
ns
capacitance from 10 pF to 400 pF
(1)
In Master mode the maximum I2C clock rate is 375 kHz.
(2)
A Fast-mode I2C bus device can be used in a Standard-mode I2C bus system, but the requirement tSU;DAT 250 ns must then be met.
This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the
LOW period of the SCL signal, it must output the next data bit to the SDA line.
(3)
Cb = total capacitance of one bus line in pF.
(4)
I/O pins of Fast-mode devices must not obstruct the SDA and SCL lines if VDD is switched off.
(5)
The maximum tf for the SDA and SCL bus lines (300 ns) is longer than the specified maximum tof for the output stages (250 ns). This
allows series protection resistors (Rs) to be connected between the SDA/SCL pins and the SDA/SCL bus lines without exceeding the
maximum specified tf.
Copyright 2008, Texas Instruments Incorporated
47
Product Folder Link(s): TAS3218
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