List of Illustrations
4
November 2002
SLES044B
5.1
Absolute Maximum Ratings Over Operat-
ing Temperature Ranges . . . . . . . . . . . . . .
29
Recommended Operating Conditions (Fs
= 48 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . .
29
Electrical Characteristics Over Recom-
mended Operating Conditions . . . . . . . . .
29
5.3.1
Static Digital Specifications
Over Recommended Operat-
ing Conditions . . . . . . . . . . . . .
29
5.3.2
Digital Interpolation Filter and
PWM Modulator Over Recom-
mended Operating Conditions
Fs = 48 kHz . . . . . . . . . . . . . . .
29
5.3.3
TAS5036/TAS5100 System
Performance Measured at the
Speaker Terminals Over
Recommended Operating
Conditions . . . . . . . . . . . . . . . . .
30
5.2
5.3
5.4
Switching Characteristics . . . . . . . . . . . . .
30
5.4.1
Command Sequence Timing .
30
5.4.2
Serial Audio Port . . . . . . . . . . .
34
5.4.3
Serial Control Port
—
I2C Op-
eration . . . . . . . . . . . . . . . . . . . .
37
6
Application Information . . . . . . . . . . . . . . . . . . . .
38
6.1
Serial Audio Interface Clock Master and
Slave Interface Configuration . . . . . . . . . .
39
6.1.1
Slave Configuration . . . . . . . . .
39
6.1.2
Master Configuration . . . . . . .
39
Appendix A
—
Volume Table . . . . . . . . . . . . . . . . . . . .
41
List of Illustrations
Title
Figure
2
–
1 Crystal Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8
Page
2
–
2 External PLL Loop Filter . . . . . . . . . . . . . . . . . . . .
10
2
–
3 I2S 64-Fs Format . . . . . . . . . . . . . . . . . . . . . . . . . .
11
2
–
4 I2S 48-Fs Format . . . . . . . . . . . . . . . . . . . . . . . . . .
12
2
–
5 Left-Justified 64-Fs Format . . . . . . . . . . . . . . . . . .
12
2
–
6 Left-Justified 48-Fs Format . . . . . . . . . . . . . . . . . .
13
2
–
7 Right-Justified 64-Fs Format . . . . . . . . . . . . . . . . .
13
2
–
8 Right-Justified 48-Fs Format . . . . . . . . . . . . . . . . .
14
2
–
9 DSP Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14
2
–
10 Attenuation Curve . . . . . . . . . . . . . . . . . . . . . . . . .
17
2
–
11 De-Emphasis Filter Characteristics . . . . . . . . . .
19
2
–
12 PWM Outputs and H-Bridge Driven in BTL
Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . .
21
2
–
13 Typical I2C Sequence . . . . . . . . . . . . . . . . . . . . .
22
2
–
14 Single Byte Write Transfer . . . . . . . . . . . . . . . . .
22
2
–
15 Multiple Byte Write Transfer . . . . . . . . . . . . . . . .
23
2
–
16 Single Byte Read . . . . . . . . . . . . . . . . . . . . . . . . .
23
2
–
17 Multiple Byte Read . . . . . . . . . . . . . . . . . . . . . . . .
23
4
–
1 RESET During System Initialization . . . . . . . . . . .
28
5
–
1 RESET Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
30
5
–
2 Power-Down and Power-Up Timing
—
RESET
Preceding PDN . . . . . . . . . . . . . . . . . . . . . . . . .
31
5
–
3 Power-Down and Power-Up Timing
—
RESET
Following PDN . . . . . . . . . . . . . . . . . . . . . . . . . .
32
5
–
4 Error Recovery Timing . . . . . . . . . . . . . . . . . . . . . .
33