參數(shù)資料
型號: TAS5414ATPHDQ1
廠商: TEXAS INSTRUMENTS INC
元件分類: 音頻/視頻放大
英文描述: 116 W, 4 CHANNEL, AUDIO AMPLIFIER, PQFP64
封裝: GREEN, PLASTIC, HTQFP-64
文件頁數(shù): 16/54頁
文件大小: 1386K
代理商: TAS5414ATPHDQ1
A6
A5
A0 R/W ACK A7
A6
A5
A4
A0 ACK
A6
A5
A0
ACK
Start
Condition
Stop
Condition
Acknowledge
I CDevice Addressand
2
Read/WriteBit
Subaddress
DataByte
D7
D6
D1
D0 ACK
I CDevice Addressand
Read/WriteBit
2
Not
Acknowledge
R/W
A1
RepeatStart
Condition
T0036-03
A6
A0
ACK
Acknowledge
I CDevice Addressand
Read/WriteBit
2
R/W
A6
A0
R/W ACK
A0 ACK
D7
D0
ACK
Start
Condition
Stop
Condition
Acknowledge
LastDataByte
ACK
FirstDataByte
RepeatStart
Condition
Not
Acknowledge
I CDevice Addressand
Read/WriteBit
2
Subaddress
OtherDataBytes
A7
A6
A5
D7
D0 ACK
Acknowledge
D7
D0
T0036-04
SLOS535C
– MAY 2009 – REVISED APRIL 2011
Random Read
As shown in Figure 19, a single-byte data-read transfer begins with the master device transmitting a start
condition followed by the I2C device address and the read/write bit. For the data-read transfer, both a write
followed by a read are actually done. Initially, a write is done to transfer the address byte or bytes of the internal
memory address to be read. As a result, the read/write bit is a 0. After receiving the address and the read/write
bit, the TAS5414A or TAS5424A responds with an acknowledge bit. In addition, after sending the internal
memory address byte or bytes, the master device transmits another start condition followed by the TAS5414A or
TAS5424A address and the read/write bit again. This time the read/write bit is a 1, indicating a read transfer.
After receiving the address and the read/write bit, the TAS5414A or TAS5424A again responds with an
acknowledge bit. Next, the TAS5414A or TAS5424A transmits the data byte from the memory address being
read. After receiving the data byte, the master device transmits a not-acknowledge followed by a stop condition
to complete the single-byte data-read transfer.
Figure 19. Random Read Transfer
Sequential Read
A sequential data-read transfer is identical to a single-byte data-read transfer except that multiple data bytes are
transmitted by the TAS5414A or TAS5424A to the master device as shown in Figure 20. Except for the last data
byte, the master device responds with an acknowledge bit after receiving each data byte and automatically
increments the I2C subaddress by one. Note: The fault registers do not have sequential read capabilities.
Figure 20. Sequential Read Transfer
Copyright
2009–2011, Texas Instruments Incorporated
23
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