參數(shù)資料
型號(hào)： TAS5414TDKDRMQ1G4
廠商： TEXAS INSTRUMENTS INC
元件分類： 音頻／視頻放大
英文描述： 116 W, 4 CHANNEL, AUDIO AMPLIFIER, PDSO36
封裝： GREEN, PLASTIC, HSSOP-36
文件頁(yè)數(shù)： 39/43頁(yè)
文件大?。?/td> 978K
代理商： TAS5414TDKDRMQ1G4
www.ti.com
SLOS514A – FEBRUARY 2007 – REVISED JULY 2007
Table 1. TERMINAL FUNCTIONS
TERMINAL
DKD Package
TYPE(1)
DESCRIPTION
NAME
TAS5414 TAS5424
NO.
A_BYP
13
14
PBY
Bypass capacitor for the AVDD analog regulator
Open-drain CLIP, OTW, or logical OR of the CLIP and OTW outputs. It also reports
CLIP_OTW
9
10
DO
tweeter detection during tweeter mode.
CP
28
34
CP
Top of main storage capacitor for charge pump (bottom goes to PVDD)
CPC_BOT
27
33
CP
Bottom of flying capacitor for charge pump
CPC_TOP
29
35
CP
Top of flying capacitor for charge pump
D_BYP
8
9
PBY
Bypass pin for DVDD regulator output
FAULT
5
DO
Global fault output (open drain): UV, OV, OTSD, OCSD, DC
GND
10
7, 11
DG
Ground
I2C_ADDR
2
AI
I2C address bit
IN1_M
N/A
16
AI
Inverting analog input for channel 1 (TAS5424 only)
IN1_P
14
15
AI
Non-inverting analog input for channel 1
IN2_M
N/A
18
AI
Inverting analog input for channel 2 (TAS5424 only)
IN2_P
15
17
AI
Non-inverting analog input for channel 2
IN3_M
N/A
20
AI
Inverting analog input for channel 3 (TAS5424 only)
IN3_P
17
19
AI
Non-inverting analog input for channel 3
IN4_M
N/A
22
AI
Inverting analog input for channel 4 (TAS5424 only)
IN4_P
18
21
AI
Non-inverting analog input for channel 4
IN_M
16
N/A
ARTN
Signal return for the 4 analog channel inputs (TAS5414 only)
MUTE
6
AI
Gain ramp control: mute (low), play (high)
Oscillator sync input from master or output to slave amplifiers (20 MHz divided by 5,
OSC_SYNC
1
DI/DO
6, or 7)
OUT1_M
34
41
PO
– polarity output for bridge 1
OUT1_P
33
40
PO
+ polarity output for bridge 1
OUT2_M
31
37
PO
– polarity output for bridge 2
OUT2_P
30
36
PO
+ polarity output for bridge 2
OUT3_M
25
31
PO
– polarity output for bridge 3
OUT3_P
24
30
PO
+ polarity output for bridge 3
OUT4_M
22
27
PO
– polarity output for bridge 4
OUT4_P
21
26
PO
+ polarity output for bridge 4
28, 29,
23, 26,
PGND
32, 38,
PGND
Power GND
32
39
23, 24,
19, 20,
PVDD
25, 42,
PWR
PVDD supply
35, 36
43, 44
REXT
12
13
AI
Precision resistor pin to set clock frequency
SCL
4
DI
I2C clock input from system I2C master
SDA
3
DI/DO
I2C data I/O for communication with system I2C master
SGND
11
12
AG/DG
Signal ground (analog and digital signal ground)
STANDBY
7
8
DI
Active-low STANDBY pin. Standby (low), power up (high)
(1)
DI = digital input, DO = digital output, AI = analog input, ARTN = analog signal return, PWR = power supply, PGND = power ground,
PBY = power bypass, PO = power output, AG = analog ground, DG = digital ground, CP = charge pump.
5
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