SLOS535B – MAY 2009 – REVISED JANUARY 2010
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ELECTRICAL CHARACTERISTICS (continued)
Test conditions (unless otherwise noted): TCase = 25°C, PVDD = 14.4 V, RL = 4 , fS = 417 kHz, Pout = 1 W/ch, Rext = 20 k,
AES17 Filter, master mode operation (see application diagram)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VA_BYP
A_BYP pin voltage
6.5
V
VA_BYP_UV_SET
A_BYP UV voltage
4.8
V
VA_BYP_UV_CLEAR
Recovery voltage A_BYP UV
5.3
V
DVDD
VD_BYP
D_BYP pin voltage
3.3
V
POWER-ON RESET (POR)
Maximum PVDD voltage for POR; I2C active
VPOR
6
V
above this voltage
VPOR_HY
PVDD recovery hysteresis voltage for POR
0.1
V
REXT
VREXT
Rext pin voltage
1.24
V
CHARGE PUMP (CP)
VCPUV_SET
CP undervoltage
4.8
V
VCPUV_CLEAR
Recovery voltage for CP UV
5.2
V
OVERTEMPERATURE (OT) PROTECTION
TOTW1_CLEAR
102
115
128
TOTW1_SET /
112
125
138
TOTW2_CLEAR
Junction temperature for overtemperature
TOTW2_SET /
warning
122
135
148
TOTW3_CLEAR
°C
TOTW3_SET /
132
145
158
TOTSD_CLEAR
Junction temperature for overtemperature
TOTSD
142
155
168
shutdown
CURRENT LIMITING PROTECTION
ILIM1
Current limit 1 (load current)
Load < 4
5.5
7.3
9
A
Current limit 2 (load current), through I2C
ILIM2
Load < 2
8.5
11
13.5
A
setting
OVERCURRENT (OC) SHUTDOWN PROTECTION
IMAX1
Maximum current 1 (peak output current)
9.5
11.3
13
A
Any short to supply, ground, or other channels
IMAX2
Maximum current 2 (peak output current)
11.5
14.3
17
A
TWEETER DETECT
ITH_TW
Load current threshold for tweeter detect
325
540
750
mA
ILIM_TW
Load current limit for tweeter detect
2
A
STANDBY MODE
VIH_STBY
STANDBY input voltage for logic-level high
2
5.5
V
VIL_STBY
STANDBY input voltage for logic-level low
0
0.7
V
ISTBY_PIN
STANDBY pin current
0.1
0.2
mA
MUTE MODE
GMUTE
Output attenuation
MUTE pin
≤ 0.9 Vdc, VIN = 1 Vrms on all inputs
85
dB
DC DETECT
VTH_DCD_POS
DC detect positive threshold default value
PVDD = 14.4 Vdc, register 0x0E = 8EH
6.5
V
VTH_DCD_NEG
DC detect negative threshold default value
PVDD = 14.4 Vdc, register 0x0F = 3DH
–6.5
V
DC detect step response time for four
tDCD
4.3
s
channels
CLIP_OTW REPORT
CLIP_OTW pin output voltage for logic level
VOH_CLIPOTW
2.4
V
high (open-drain logic output)
External 47-k
pullup resistor to 3 V–5.5 V
CLIP_OTW pin output voltage for logic level
VOL_CLIPOTW
0.5
V
low (open-drain logic output)
CLIP_OTW signal delay when output
tDELAY_CLIPDET
20
ms
clipping detected
10
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