參數(shù)資料
型號(hào)： TAS5504PAGG4
廠商： TEXAS INSTRUMENTS INC
元件分類(lèi)： 消費(fèi)家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PQFP64
封裝： GREEN, PLASTIC, TQFP-64
文件頁(yè)數(shù)： 39/96頁(yè)
文件大?。?/td> 1216K
代理商： TAS5504PAGG4
TAS5504 Controls and Status
37
SLES123 October 2004
TAS5504
Modulation Index Limit
Inter-channel Delay
Master Clock and Data Rate Controls
Bank Controls
2.3.1 Channel Configuration Registers
In order for the TAS5504 to have full control of the power stages, registers 0x05, 0x06, 0x0B, and 0x0C must
be programmed to reflect the proper power stage and how each one should be controlled. Channel
configuration registers consist of four registers, one for each channel.
The primary reason for using these registers is that different power stages require different handling during
start up, mute/unmute, shutdown, and error recovery. The TAS5504 must select the sequence that gives the
best click and pop performance and insure that the bootstrap capacitor is charged correctly during start up.
This sequence depends on which power stage is present at the TAS5504 output.
Table 25. Description of the Channel Configuration Registers (0x05, 0x06, 0x0B, 0x0C)
BIT
DESCRIPTION
D7
Enable/disable error recovery sequence. In case the BKND_RECOVERY pin is pulled low, this register determines if this channel is
to follow the error recovery sequence or to continue with no interruption.
D6
Determines if the power stage needs the TAS5504 VALID pin to go low to reset the power stage. Some power stages can be reset
by a combination of PWM signals. For these devices, it is recommended to set this bit low, since the VALID pin is shared for power
stages. This provides better control of each power stage.
D5
Determines if the power stage needs the TAS5504 VALID pin to go low to mute the power stage. Some power stages can be muted
by a combination of PWM signals. For these devices, it is recommended to set this bit low, since the VALID pin is shared for power
stages. This provides better control of each power stage.
D4
Inverts the PWM output. Inverting the PWM output can be an advantage if the power stage input pin are opposite the TAS5504 PWM
pinout. This makes routing on the PCB easier. To keep the phase of the output the speaker terminals must also be inverted.
D3
The power stage TAS5182 has a special PWM input. To ensure that the TAS5504 has full control in all occasions, the PWM output
must be remapped.
D2
Can be used to handle click and pop for some applications.
D1
This bit is normally used together with D2. For some power stages, both PWM signals must be high to get the desired operation of
both speaker outputs to be low. This bit sets the PWM outputs high-high during mute.
D0
Not used
Table 26 lists the optimal setting for each output stage configuration. Note that the default value is applicable
in all configurations except the TAS5182 SE/BTL configuration.
Table 26. Recommended TAS5504 Configurations for Texas Instruments Power Stages
DEVICE
ERROR RECOVERY
CONFIGURATION
D7
D6
D5
D4
D3
D2
D1
D0
Default
RES
BTL
1
0
RES
BTL
1
0
TAS5111
RES
SE
1
0
TAS5111
AUT
BTL
0
1
0
AUT
SE
0
1
0
RES
BTL
1
0
TAS5112
RES
SE
1
0
TAS5112
AUT
BTL
0
1
0
AUT
SE
0
1
0
TAS5182
RES
BTL
1
0
1
0
TAS5182
RES
SE
1
0
1
0
RES: The output stage requires VALID to go low to recover from a shutdown.
AUT: The power stage can auto recover from a shutdown.
BTL: Bridge tied load configuration
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