TAS5508B
8-Channel Digital Audio PWM Processor
www.ti.com
SLES162C – DECEMBER 2005 – REVISED JULY 2009
3.2.2
Power Down (PDN)
.............................................................................................
443.2.3
Back-End Error (BKND_ERR)
.................................................................................
443.2.3.1
BKND_ERR and VALID
..............................................................................
453.2.4
Speaker/Headphone Selector (HP_SEL)
.....................................................................
453.2.5
Mute (MUTE)
.....................................................................................................
453.3
Device Configuration Controls
............................................................................................
463.3.1
Channel Configuration Registers
..............................................................................
463.3.2
Headphone Configuration Registers
..........................................................................
473.3.3
Audio System Configurations
..................................................................................
473.3.3.1
Using Line Outputs in 6-Channel Configurations
.................................................
483.3.4
Recovery from Clock Error
.....................................................................................
483.3.5
Power-Supply Volume-Control Enable
.......................................................................
483.3.6
Volume and Mute Update Rate
................................................................................
483.3.7
Modulation Index Limit
..........................................................................................
483.4
Master Clock and Serial Data Rate Controls
...........................................................................
493.4.1
PLL Operation
....................................................................................................
493.5
Bank Controls
...............................................................................................................
493.5.1
Manual Bank Selection
.........................................................................................
503.5.2
Automatic Bank Selection
......................................................................................
503.5.2.1
Coefficient Write Operations While Automatic Bank Switch Is Enabled
.......................
503.5.3
Bank Set
..........................................................................................................
503.5.4
Bank-Switch Timeline
...........................................................................................
513.5.5
Bank-Switching Example 1
.....................................................................................
513.5.6
Bank-Switching Example 2
.....................................................................................
514
Electrical Specifications
...................................................................................................... 52 4.1
Absolute Maximum Ratings
...............................................................................................
524.2
Dissipation Rating Table (High-k Board, 105
°C Junction) ................................................. 52 4.3
Dynamic Performance at Recommended Operating Conditions at 25
°C................................ 52 4.4
Recommended Operating Conditions
........................................................................
524.5
Electrical Characteristics
.......................................................................................
534.6
PWM Operation
..................................................................................................
534.7
Switching Characteristics
.......................................................................................
534.7.1
Clock Signals
.....................................................................................................
534.7.2
Serial Audio Port
.................................................................................................
544.7.3
TAS5508B Pin-Related Characteristics of the SDA and SCL I/O Stages for F/S-Mode I
2C-Bus
Devices
...........................................................................................................
544.7.4
TAS5508B Bus-Related Characteristics of the SDA and SCL I/O Stages for F/S-Mode I
2C-Bus
Devices
...........................................................................................................
554.7.4.1
Recommended I
2C Pullup Resistors
...............................................................
564.7.5
Reset Timing (RESET)
.........................................................................................
574.7.6
Power-Down (PDN) Timing
....................................................................................
574.7.7
Back-End Error (BKND_ERR)
.................................................................................
584.7.8
Mute Timing (MUTE)
............................................................................................
584.7.9
Headphone Select (HP_SEL)
..................................................................................
594.7.10
Volume Control
..................................................................................................
594.8
Serial Audio Interface Control and Timing
...................................................................
604.8.1
I
2S Timing
........................................................................................................
604.8.2
Left-Justified Timing
.............................................................................................
614.8.3
Right-Justified Timing
...........................................................................................
625
I2C Serial-Control Interface (Slave Addresses 0x36 and 0x37)
.................................................. 63 5.1
General I
2C Operation
.....................................................................................................
635.2
Single- and Multiple-Byte Transfers
.....................................................................................
645.3
Single-Byte Write
...........................................................................................................
64Contents
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