參數(shù)資料
型號： TAS5615DKD2EVM
廠商： Texas Instruments
文件頁數(shù)： 31/36頁
文件大?。?/td> 0K
描述： EVAL MODULE FOR TAS5615
標準包裝： 1
系列： *
SLAS595B – JUNE 2009 – REVISED FEBRUARY 2010
www.ti.com
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted
(1)
TAS5615
UNIT
VDD to AGND
–0.3 to 13.2
V
GVDD to AGND
–0.3 to 13.2
V
PVDD_X to GND_X(2)
–0.3 to 69.0
V
OUT_X to GND_X(2)
–0.3 to 69.0
V
BST_X to GND_X(2)
–0.3 to 82.2
V
BST_X to GVDD_X(2)
–0.3 to 69.0
V
VREG to AGND
–0.3 to 4.2
V
GND_X to GND
–0.3 to 0.3
V
GND_X to AGND
–0.3 to 0.3
V
OC_ADJ, M1, M2, M3, OSC_IO+, OSC_IO–, FREQ_ADJ, VI_CM, C_STARTUP,
–0.3 to 4.2
V
PSU_REF to AGND
INPUT_X
–0.3 to 5
V
RESET, SD, OTW1, OTW2, CLIP, READY to AGND
–0.3 to 7.0
V
Continuous sink current (SD, OTW1, OTW2, CLIP, READY)
9
mA
Operating junction temperature range, TJ
0 to 150
°C
Storage temperature, Tstg
–40 to 150
°C
Human-body model(3) (all pins)
±2
kV
Electrostatic discharge
Charged-device model(3) (all pins)
±500
V
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2)
These voltages represent the dc voltage + peak ac waveform measured at the terminal of the device in all conditions.
(3)
Failure to follow good anti-static ESD handling during manufacture and rework contributes to device malfunction. Make sure the
operators handling the device are adequately grounded through the use of ground straps or alternative ESD protection.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN NOM
MAX
UNIT
PVDD_x
Half-bridge supply
DC supply voltage
25
50
52.5
V
Supply for logic regulators and gate-drive
GVDD_x
DC supply voltage
10.8
12
13.2
V
circuitry
VDD
Digital regulator supply voltage
DC supply voltage
10.8
12
13.2
V
RL(BTL)
7
8.0
Output filter according to schematics in
RL(SE)
Load impedance
3.5
4.0
the application information section.
RL(PBTL)
3.5
4.0
LOUTPUT(BTL)
14
15
LOUTPUT(SE)
Output filter inductance
Minimum output inductance at IOC
14
15
mH
LOUTPUT(PBTL)
14
15
Nominal
385
400
415
PWM frame rate selectable for AM interference
fPWM
AM1
315
333
350
kHz
avoidance; 1% resistor tolerance
AM2
260
300
335
Nominal; master mode
9.9
10
10.1
RFREQ_ADJ
PWM frame-rate programming resistor
AM1; master mode
19.8
20
20.2
k
AM2; master mode
29.7
30
30.3
Voltage on FREQ_ADJ pin for slave mode
VFREQ_ADJ
Slave mode
3.3
operation
TJ
Junction temperature
0
150
°C
4
Copyright 2009–2010, Texas Instruments Incorporated
Product Folder Link(s) :TAS5615
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