- 您現在的位置：買賣IC網 > PDF目錄98165 > TAS5719PHPR (TEXAS INSTRUMENTS INC) 15 W, 2 CHANNEL, AUDIO AMPLIFIER, PQFP48 PDF資料下載
參數資料
| 型號： | TAS5719PHPR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 音頻／視頻放大 |
| 英文描述： | 15 W, 2 CHANNEL, AUDIO AMPLIFIER, PQFP48 |
| 封裝： | 7 X 7 MM, GREEN, PLASTIC, HTQFP-48 |
| 文件頁數： | 20/67頁 |
| 文件大?。?/td> | 1043K |
| 代理商： | TAS5719PHPR |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁當前第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁
7-BitSlave Address
R/
W
8-BitRegister Address(N)
A
8-BitRegisterDataFor
Address(N)
Start
Stop
SDA
SCL
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
A
8-BitRegisterDataFor
Address(N)
A
T0035-01
SLOS655A
– NOVEMBER 2010 – REVISED FEBRUARY 2011
I
2C SERIAL CONTROL INTERFACE
The TAS5717/9 DAP has a bidirectional I2C interface that is compatible with the Inter IC (I2C) bus protocol and
supports both 100-kHz and 400-kHz data transfer rates for single- and multiple-yte write and read operations.
This is a slave-only device that does not support a multimaster bus environment or wait-state insertion. The
control interface is used to program the registers of the device and to read device status.
The DAP supports the standard-mode I2C bus operation (100 kHz maximum) and the fast I2C bus operation
(400 kHz maximum). The DAP performs all I2C operations without I2C wait cycles.
General I2C Operation
The I2C bus employs two signals; SDA (data) and SCL (clock), to communicate between integrated circuits in a
system. Data is transferred on the bus serially, one bit at a time. The address and data can be transferred in byte
(8-bit) format, with the most significant bit (MSB) transferred first. In addition, each byte transferred on the bus is
acknowledged by the receiving device with an acknowledge bit. Each transfer operation begins with the master
device driving a start condition on the bus and ends with the master device driving a stop condition on the bus.
The bus uses transitions on the data pin (SDA) while the clock is high to indicate start and stop conditions. A
high-to-low transition on SDA indicates a start and a low-to-high transition indicates a stop. Normal data-bit
transitions must occur within the low time of the clock period. These conditions are shown in Figure 35. The
master generates the 7-bit slave address and the read/write (R/W) bit to open communication with another
device and then waits for an acknowledge condition. The TAS5717/9 holds SDA low during the acknowledge
clock period to indicate an acknowledgment. When this occurs, the master transmits the next byte of the
sequence. Each device is addressed by a unique 7-bit slave address plus R/W bit (1 byte). All compatible
devices share the same signals via a bidirectional bus using a wired-AND connection. An external pullup resistor
must be used for the SDA and SCL signals to set the high level for the bus.
Figure 35. Typical I2C Sequence
There is no limit on the number of bytes that can be transmitted between start and stop conditions. When the last
word transfers, the master generates a stop condition to release the bus. A generic data transfer sequence is
shown in Figure 35.
The 7-bit address for TAS5717/9 is 0101 010 (0x54) or 0101 011 (0x56) defined by A_SEL (external pulldown for
0x54 and pullup for 0x56).Stero device with Headphone should use 0x54 as its device address.
Single- and Multiple-Byte Transfers
The serial control interface supports both single-byte and multiple-byte read/write operations for subaddresses
0x00 to 0x1F. However, for the subaddresses 0x20 to 0xFF, the serial control interface supports only
multiple-byte read/write operations (in multiples of 4 bytes).
During multiple-byte read operations, the DAP responds with data, a byte at a time, starting at the subaddress
assigned, as long as the master device continues to respond with acknowledges. If a particular subaddress does
not contain 32 bits, the unused bits are read as logic 0.
During multiple-byte write operations, the DAP compares the number of bytes transmitted to the number of bytes
that are required for each specific subaddress. For example, if a write command is received for a biquad
subaddress, the DAP expects to receive five 32-bit words. If fewer than five 32-bit data words have been
received when a stop command (or another start command) is received, the data received is discarded.
2010–2011, Texas Instruments Incorporated
27
相關PDF資料 |
PDF描述 |
|---|---|
| TAS5719PHP | 15 W, 2 CHANNEL, AUDIO AMPLIFIER, PQFP48 |
| TB1212N | SPECIALTY CONSUMER CIRCUIT, PDIP64 |
| TB1212F | SPECIALTY CONSUMER CIRCUIT, PQFP80 |
| TB1226DNG | SPECIALTY CONSUMER CIRCUIT, PDIP56 |
| TB1226DN | SPECIALTY CONSUMER CIRCUIT, PDIP56 |
相關代理商/技術參數 |
參數描述 |
|---|---|
| TAS5720LRSMT | 功能描述:Amplifier IC 1-Channel (Mono) Class D 32-VQFN (4x4) 制造商:texas instruments 系列:- 包裝:剪切帶（CT） 零件狀態(tài):有效 類型:D 類 輸出類型:1-通道（單聲道） 不同負載時的最大輸出功率 x 通道數:20W x 1 @ 4 歐姆 電壓 - 電源:4.5 V ~ 16.5 V 特性:消除爆音，短路和熱保護 安裝類型:表面貼裝 工作溫度:-25°C ~ 85°C（TA） 供應商器件封裝:32-VQFN（4x4） 封裝/外殼:32-VFQFN 裸露焊盤 標準包裝:1 |
| TAS5720MEVM | 功能描述:TAS5720M - 1-Channel (Mono) Output Class D Audio Amplifier Evaluation Board 制造商:texas instruments 系列:- 零件狀態(tài):有效 放大器類型:D 類 輸出類型:1-通道（單聲道） 不同負載時的最大輸出功率 x 通道數:15W x 1 @ 4 歐姆 電壓 - 電源:4.5 V ~ 26.4 V 板類型:完全填充 使用的 IC/零件:TAS5720M 所含物品:板 標準包裝:1 |
| TAS5720MRSMT | 功能描述:Amplifier IC 1-Channel (Mono) Class D 32-VQFN (4x4) 制造商:texas instruments 系列:- 包裝:剪切帶（CT） 零件狀態(tài):有效 類型:D 類 輸出類型:1-通道（單聲道） 不同負載時的最大輸出功率 x 通道數:20W x 1 @ 4 歐姆 電壓 - 電源:4.5 V ~ 26.4 V 特性:消除爆音，短路和熱保護 安裝類型:表面貼裝 工作溫度:-25°C ~ 85°C（TA） 供應商器件封裝:32-VQFN（4x4） 封裝/外殼:32-VFQFN 裸露焊盤 標準包裝:1 |
| TAS5721 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Digital Audio Power Amplifier with EQ, DRC, 2.1 Support, and Headphone/Line Driver |
| TAS5721DCA | 功能描述:音頻放大器 15W Stereo Class-D Audio Amp RoHS:否 制造商:STMicroelectronics 產品:General Purpose Audio Amplifiers 輸出類型:Digital 輸出功率: THD + 噪聲: 工作電源電壓:3.3 V 電源電流: 最大功率耗散: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:TQFP-64 封裝:Reel |
發(fā)布緊急采購，3分鐘左右您將得到回復。