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參數(shù)資料
| 型號： | TB1311AFG |
| 元件分類： | 信號分離 |
| 英文描述： | SYNC SEPARATOR IC, PQFP80 |
| 封裝： | 14 X 20 MM, 0.80 MM PITCH, PLASTIC, QFP-80 |
| 文件頁數(shù)： | 24/46頁 |
| 文件大?。?/td> | 948K |
| 代理商： | TB1311AFG |
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TB1311AFG
2006-05-29
30
Data Transmit Format 1
Data Transmit Format 2
Data Receive Format
To receive data, the master transmitter changes to a receiver immediately after the first acknowledgement.
The slave receiver changes to a transmitter.
The end condition is always created by the master.
Optional Data Transmit Format (Automatic Increment Mode)
In this way, sub-addresses are automatically incremented from the specified sub-address and data are set.
I
2CBUS Conditions
Parameter
Symbol
Min
Typ.
Max
Unit
Low level input voltage
VIL
0
1.1
V
High level input voltage
VIH
2.4
V/S-Vcc
V
Hysteresis of Schmitt trigger inputs
Vhys
0.7
V
Low level output voltage at 3 mA sink current
VOL1
0
0.4
V
Input current each I/O pin with an input voltage
between 0.1 VDD and 0.9 VDD
Ii
-10
10
A
Capacitance for each I/O pin
Ci
10
pF
SCL clock frequency
fSCL
0
400
kHz
Hold time START condition
tHD;STA
0.6
s
Low period of SCL clock
tLOW
1.3
s
High period of SCL clock
tHIGH
0.6
s
Set-up time for a repeated START condition
tSU;STA
0.6
s
Data hold time
tHD;DAT
0
ns
Data set-up time
tSU;DAT
100
ns
Set-up time for STOP condition
tSU;STO
0.6
s
Bus free time between a STOP and START condition
tBUF
1.3
s
Note: This parameter is not tested during production and is provided only as information to assist the design of applications.
S
Slave address
0 A
Transmit data 1
A
Sub-address
A
Transmit data n
A
Sub-address
A P
S
Slave address
0 A
Transmit data
A
Sub-address
A P
7-bit
MSB
S: Start condition
8-bit
MSB
A: Acknowledgement
8-bit
MSB
P: End condition
S
Slave address
1 A
Receive data n
Receive data 1
A P
7-bit
MSB
8-bit
MSB
S
Slave address
A
Transmit data n
Transmit data 1
A P
7-bit
MSB
8-bit
MSB
0
Sub-address
7-bit
MSB
A 1
8-bit
MSB
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