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  • 參數(shù)資料
    型號(hào): TB28F800BV-T80
    廠商: INTEL CORP
    元件分類: DRAM
    英文描述: 2-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY
    中文描述: 1M X 8 FLASH 5V PROM, 80 ns, PDSO44
    封裝: 0.525 X 1.110 INCH, PLASTIC, SOP-44
    文件頁(yè)數(shù): 52/55頁(yè)
    文件大?。?/td> 638K
    代理商: TB28F800BV-T80
    2-MBIT SmartVoltage BOOT BLOCK FAMILY
    E
    52
    SEE NEW DESIGN RECOMMENDATIONS
    4.14
    AC Characteristics
    —CE#-Controlled Write Operations
    (1, 11)
    Extended Temperature
    Prod
    TBV-80
    TBV-80
    TBE-120
    Sym
    Parameter
    V
    CC
    3.3 ±0.3 V
    (9)
    5 V±10%
    (10)
    Unit
    Load
    50 pF
    100 pF
    Notes
    Min
    Max
    Min
    Max
    t
    AVAV
    t
    PHEL
    Write Cycle Time
    110
    80
    ns
    RP# High Recovery to CE# Going Low
    0.8
    0.45
    μ
    s
    t
    WLEL
    t
    PHHEH
    t
    VPEH
    t
    AVEH
    t
    DVEH
    t
    ELEH
    t
    EHDX
    t
    EHAX
    t
    EHWH
    t
    EHEL
    t
    EHQV1
    WE# Setup to CE# Going Low
    0
    0
    ns
    Boot Block Lock Setup to CE# Going High
    6,8
    200
    100
    ns
    V
    PP
    Setup to CE# Going High
    Address Setup to CE# Going High
    5,8
    200
    100
    ns
    90
    60
    ns
    Data Setup to CE# Going High
    3
    70
    60
    ns
    CE# Pulse Width
    4
    90
    60
    ns
    Data Hold Time from CE# High
    0
    0
    ns
    Address Hold Time from CE# High
    4
    0
    0
    ns
    WE# Hold Time from CE# High
    3
    0
    0
    ns
    CE# Pulse Width High
    20
    20
    ns
    Word/Byte Program Time
    2,5
    6
    6
    μs
    t
    EHQV2
    Erase Duration (Boot)
    2,5,6
    0.3
    0.3
    s
    t
    EHQV3
    Erase Duration (Param)
    2,5
    0.3
    0.3
    s
    t
    EHQV4
    Erase Duration (Main)
    2,5
    0.6
    0.6
    s
    t
    QVVL
    t
    QVPH
    t
    PHBR
    NOTES:
    See AC Characteristics
    —WE#-Controlled Write Operations
    for notes 1 through 10.
    11. Chip-Enable controlled writes: write operations are driven by the valid combination of CE# and WE# in systems where CE#
    defines the write pulse-width (within a longer WE# timing waveform), all set-up, hold and inactive WE# times should be
    measured relative to the CE# waveform.
    V
    PP
    Hold from Valid SRD
    RP# V
    HH
    Hold from Valid SRD
    Boot-Block Lock Delay
    5,8
    0
    0
    ns
    6,8
    0
    0
    ns
    7,8
    200
    100
    ns
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