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參數(shù)資料
| 型號： | TB31356AFL |
| 廠商： | Toshiba Corporation |
| 英文描述： | 1.8GHz,600MHz DUAL-PLL FREQUENCY SYNTHESIZER |
| 中文描述： | 配備1.8GHz，600MHz的雙鎖相環(huán)頻率合成器 |
| 文件頁數(shù)： | 7/10頁 |
| 文件大?。?/td> | 297K |
| 代理商： | TB31356AFL |
TENTATIVE TB31356AFL
l
This specification is design target. It is subject to change without notice
.
Nov. 27 2002 PAGE 7
Lock detection
A signal indicating whether the PLL has phase-locked to the desired frequency is presented to the LD pin.
The PLL to be detected in this way can be selected by setting two bits, LD1 and LD2, as shown in the table
below.
LD1
LD2
Detected PLL
0
0
Not detected (fixed low)
0
1
PLL2
1
0
PLL1
1
1
Only when both PLL1 and PLL2 are
detected
Locked in phase = open, Unlocked = low, Power-down mode = open
l
Power-down mode
The PLL1, PLL2, and crystal oscillator circuit can be switched between operating and power-down
modes by using three bits—SB1, SB2, and SBX. The table below shows how operation is controlled by using
these bits and external battery save pins.
External Pin
BS1
L
L
H
H
H
H
H
H
Serial Data
SB2
*
*
*
0
0
1
0
1
Operation State
PLL2
OFF
ON
OFF
OFF
OFF
ON
OFF
ON
BS2
L
H
L
H
H
H
H
H
SB1
*
*
*
0
0
0
1
1
SBX
*
*
*
0
1
*
*
*
PLL1
OFF
OFF
ON
OFF
OFF
OFF
ON
ON
Buffer
OFF
ON
ON
OFF
ON
ON
ON
ON
Notes1 : ON : operating, OFF : power-down (not operating), * : don’t care
Notes2 : Switching between operating and battery saving (power down) mode by using serial data is
renewed at the rising edge of strobe signal.
Notes3 : Switching between operating and battery saving (power down) mode by using external pin
(BS-PLL1,BS-PLL2) is controlled real-time.
Notes4 : Immediately after power on, need a initial setting by serial data before operation state “ON”.
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