參數(shù)資料
型號: TC1142-4.0EUATR
元件分類: 穩(wěn)壓器
英文描述: SWITCHED CAPACITOR REGULATOR, 275 kHz SWITCHING FREQ-MAX, PDSO8
封裝: MSOP-8
文件頁數(shù): 5/12頁
文件大?。?/td> 246K
代理商: TC1142-4.0EUATR
TC1142
DS21360C-page 2
2005 Microchip Technology Inc.
1.0
ELECTRICAL
CHARACTERISTICS
Absolute Maximum Ratings*
Supply Voltage (VIN) with COUT Connected ..........6.5V
CCLK Voltage................................-0.3V to (V+ + 0.3V)
Power Dissipation.............................................320mW
Operating Temperature Range
8-Pin MSOP ................................. -40°C to +85°C
Storage Temperature Range ..............-65°C to +160°C
*Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. These
are stress ratings only and functional operation of the device
at these or any other conditions above those indicated in the
operation sections of the specifications is not implied.
Exposure to Absolute Maximum Rating conditions for
extended periods may affect device reliability.
TC1142 ELECTRICAL SPECIFICATIONS
Electrical Characteristics: RL = ∞, VIN = 3.2V, Mode = -2x, C1 = C2 = 0.47μF (Note 1), CCLK = VIH, COUT = 4.7μF, for VR = 3V,
VIN = 3.5V, TA = TMIN to TMAX, unless otherwise noted.
Symbol
Parameter
Min
Typ
Max
Units
Test Conditions
VIN
Supply Voltage
2.5
5.5
V
VOUT
Output Voltage
-(VR + 0.2)
-VR
-(VR – 0.2)
V
IL = 0mA (Note 2)
VP-P
Output Ripple
100
mV
IL = 10mA
ISUPPLY
Supply Current
200
400
μA
ISUPPLY1
—0.1
1
μACCLK = 0V
ROUTCL
Closed-Loop Output Resistance
2
6
Ω
ROUT
Open-Loop Output Resistance
30
Ω
(Note 3)
fOSC
Internal Oscillator Frequency
150
200
275
kHz
fCCLK
External Clock Frequency, Typical
3
500
kHz
(Note 4)
PEFF
Power Efficiency
70
76
%
IL = 10mA, VR = 5V; (See Equation 3-5)
VIH
CCLK Input High Threshold
2.2
V
VIL
CCLK Input Low Threshold
1.0
V
Note
1:
Assume C1 and C2 have an ESR of 1
Ω.
2:
VR is the voltage output specified in the ordering option.
3:
Measured in -1x Mode. For VR = 3V, VIN = 2.5V.
4:
CCLK is driven with an external clock. Minimum frequency = 1/2t0 at 50% duty cycle, where t0 is the counter timeout period.
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