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參數(shù)資料
| 型號(hào)： | TC1271LERCG |
| 元件分類： | 電源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO4 |
| 封裝： | SOT-143, 4 PIN |
| 文件頁數(shù)： | 8/12頁 |
| 文件大?。?/td> | 498K |
| 代理商： | TC1271LERCG |
2006 Microchip Technology Inc.
DS21381C-page 5
TC1270/TC1271
3.0
APPLICATIONS INFORMATION
3.1
VCC Transient Rejection
The TC1270/TC1271 provides accurate VCC monitor-
ing and Reset timing during power-up, power-down,
and brownout/sag conditions, and rejects negative-
going transients (glitches) on the power supply line.
Figure 3-1 shows the maximum transient duration vs.
maximum negative excursion (overdrive) for glitch
rejection. Any combination of duration and overdrive
that lays under the curve will not generate a Reset
signal. Combinations above the curve are detected as
a brown-out or power-down. Transient immunity can be
improved by adding a capacitor in close proximity to the
VCC pin of the TC1270/TC1271.
FIGURE 3-1:
Maximum Transient
Duration vs. Overdrive for Glitch Rejection at
25°C
3.2
Reset Signal Integrity During
Power-Down
The TC1270 RESET output is valid to VCC = 1.0V.
Below this voltage the output becomes an “open circuit”
and does not sink current. This means CMOS logic
inputs to the
μP will be floating at an undetermined volt-
age. Most digital systems are completely shut down
well above this voltage. However, in situations where
RESET must be maintained valid to VCC = 0V, a pull-
down resistor must be connected from RESET to
ground to discharge stray capacitances and hold the
output low (Figure 3-2). This resistor value, though not
critical, should be chosen such that it does not appre-
ciably load RESET under normal operation (100 k
Ω will
be suitable for most applications). Similarly, a pull-up
resistor to VCC is required for the TC1271 to ensure a
valid high RESET for VCC below 1.1V.
FIGURE 3-2:
Ensuring RESET Valid to
VCC = 0V
3.3
Processors With Bidirectional
I/O Pins
Some
μP’s (such as Motorola 68HC11) have bidirec-
tional Reset pins. Depending on the current drive capa-
bility of the processor pin, an indeterminate logic level
may result if there is a logic conflict. This can be
avoided by adding a 4.7 k
Ω resistor in series with the
output of the TC1270/TC1271 (Figure 3-3). If there are
other components in the system which require a Reset
signal, they should be buffered so as not to load the
Reset line. If the other components are required to
follow the Reset I/O of the
μP, the buffer should be
connected as shown with the solid line.
FIGURE 3-3:
Interfacing to Bidirectional
Reset I/O
RESET COMPARATOR OVERDRIVE,
VTH - VCC (mV)
400
240
160
320
80
0
1
10
100
1000
MAXIMUM
TRANSIENT
DURA
TION
(msec)
TA = +25°C
VTH
Duration
Overdrive
VCC
TC127LMJ
TC127xR/S/T
TC1270
VCC
R1
100k
RESET
GND
TC1270
VCC
RESET
GND
RESET
GND
Buffered RESET
To Other System
Components
Buffer
μP
4.7k
VCC
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TC1271LERCTR | 功能描述:監(jiān)控電路 4-Pin uP 4.63V Reset RoHS:否 制造商:STMicroelectronics 監(jiān)測(cè)電壓數(shù): 監(jiān)測(cè)電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復(fù)位:Resettable 監(jiān)視器:No Watchdog 電池備用開關(guān):No Backup 上電復(fù)位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
| TC1271MERC | 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:4-Pin レP Reset Monitors |
| TC1271MERCTR | 功能描述:監(jiān)控電路 4-Pin uP 4.38V Reset RoHS:否 制造商:STMicroelectronics 監(jiān)測(cè)電壓數(shù): 監(jiān)測(cè)電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復(fù)位:Resettable 監(jiān)視器:No Watchdog 電池備用開關(guān):No Backup 上電復(fù)位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
| TC1271RERC | 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:4-Pin レP Reset Monitors |
| TC1271RERCTR | 功能描述:監(jiān)控電路 4-Pin uP 2.63V Reset RoHS:否 制造商:STMicroelectronics 監(jiān)測(cè)電壓數(shù): 監(jiān)測(cè)電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復(fù)位:Resettable 監(jiān)視器:No Watchdog 電池備用開關(guān):No Backup 上電復(fù)位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
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